JPS59125653A - Analog multiplexer ic - Google Patents
Analog multiplexer icInfo
- Publication number
- JPS59125653A JPS59125653A JP58000316A JP31683A JPS59125653A JP S59125653 A JPS59125653 A JP S59125653A JP 58000316 A JP58000316 A JP 58000316A JP 31683 A JP31683 A JP 31683A JP S59125653 A JPS59125653 A JP S59125653A
- Authority
- JP
- Japan
- Prior art keywords
- analog switch
- line
- output signal
- analog
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
本発明は複数のアナログ信号を選択的に出力させるため
に用いられるアナログマルチプレクサICに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog multiplexer IC used for selectively outputting a plurality of analog signals.
アナログ信号を電子的にオン・オフ(ON−OFF)す
るアナログスイッチは電子回路技術の発展やディジタル
技術の普及に伴って急速に応用範囲が拡大されてきてい
る。最も顕著な例としてに、コンピュータ制御の自動回
路のアナログ信号変換部であり、最近では後に述べるよ
うに、ラインセンサのスイッチング素子としての用途も
広Zへりっつぁる。このように、これからは多数のアナ
ログ信号を切換える用途が多くなシ、1つのICの中に
アナログスイッチアレイとそれ全選択してスイッチング
するだめのアドレスデコーダやシフトレジスタ等の駆動
回路を含んだアナログマルチプレクサTCが中心になっ
てくると思われる。まだ性能の面からは、より微小な信
号が鍋速にスイッチできることが望まれてきている。The range of applications of analog switches that electronically turn analog signals on and off (ON-OFF) is rapidly expanding with the development of electronic circuit technology and the spread of digital technology. The most notable example is the analog signal converter of computer-controlled automatic circuits, and recently, as will be described later, it has also been widely used as a switching element for line sensors. In this way, from now on there will be many applications for switching a large number of analog signals, and an analog switch array that includes an analog switch array and drive circuits such as address decoders and shift registers to select and switch all of them in one IC. It seems that multiplexer TC will play a central role. From a performance standpoint, it is desired that a smaller signal be used to switch the pot speed.
第1図にアナログマルチプレクサICのチップ構成の一
例を示す。図において1はシリコンチ。FIG. 1 shows an example of a chip configuration of an analog multiplexer IC. In the figure, 1 is silicon.
ブ、2はアナログスイッチ部、3は駆動回路部、4は出
力信号線、5はチップ上のボンティングバッド、6はボ
ンディングワイヤ、7はICのビンである。第1図に示
しだ構成はこの神の10としては一般的なものであり、
特にホンディングパノド5はチップの周辺部に置かれる
のが普通である。2 is an analog switch section, 3 is a drive circuit section, 4 is an output signal line, 5 is a bonding pad on the chip, 6 is a bonding wire, and 7 is an IC bin. The configuration shown in Figure 1 is a common one for this god.
In particular, the bonding panode 5 is usually placed at the periphery of the chip.
しかしチップの構成かこのような形になっている限り以
下に述べるようにアナログスイッチのS/N比か非常に
悪いものになってし丑う。However, as long as the chip configuration is like this, the S/N ratio of the analog switch will be very poor as described below.
このS/N比の小さい原因を明らかにするため第1図を
第2図のように書きかえる6第2図において8 &:I
、アナログスイッチとして最も一般的なFET、9はF
Jy ’rのゲートへの配線と出力信号線が交差するこ
とによって生じる線間谷;kを表わしている。第1図を
見れば分るように、駆動回路3からアナログスイッチ2
に制御信号を送るだめの配線は図示はしていないが、必
ず入力側か又は出力側の信号線と交差する。従って第2
図に示すように線m1容量を生じるわけである。この線
間容量はFT!XTをスイッチングするスイッチングパ
ルスを出力線IIIにフィードスルーさせ、出力線側に
スイッチングノイ4が入シこむ原因になることが2次元
MO8型センサの雑音解析等から知られている。In order to clarify the cause of this small S/N ratio, Figure 1 is rewritten as Figure 2.6 In Figure 2, 8 &:I
, the most common FET as an analog switch, 9 is F
It represents the interline valley k caused by the intersection of the wiring to the gate of Jy'r and the output signal line. As can be seen from Figure 1, from the drive circuit 3 to the analog switch 2
Although the wiring for sending control signals to the terminal is not shown, it always intersects with the signal line on the input side or the output side. Therefore, the second
As shown in the figure, a line m1 capacitance is generated. This line capacitance is FT! It is known from noise analysis of two-dimensional MO8 type sensors that the switching pulse for switching the XT is fed through to the output line III, causing switching noise 4 to enter the output line side.
このことを、リニアセンサをアナログマルチプレクサI
Cで走査する場合を例にとって少し評しく述べる。第3
図がその回i?64ft J戊例である。図において1
0は電源、11に、ホオトダイオード、12はアナログ
マルチプレクサIC,1,3は1=’ E ’I’ 。This can be explained by converting the linear sensor into an analog multiplexer I.
Let us briefly describe the case of scanning with C as an example. Third
The figure is that episode i? This is an example of 64ft J. In the figure 1
0 is a power supply, 11 is a photodiode, 12 is an analog multiplexer IC, 1 and 3 are 1='E 'I'.
14HFETの電極間谷−’B::、] 5は先に述べ
/こり一−トへの配線と出力信号線との紳間容五j、1
6は負荷抵抗である。jiij作は一般的な蓄41゛i
型の−1−ンサと同じように行う。第4図にゲートパル
スφGと雑音及び光信号を示す。図においてAは線間容
’Nl″15によるケートパルスのフィードスルーで、
面1問答量15と負荷抵抗16が微分回路を形Jjy、
するため微分パルスの形となっている。f3は回4’−
IK屯極間容量14によるフィードスルーで雑音のIQ
定数の違いは容量の大きさの違いによるものである。14 HFET electrode valley B::,] 5 is the distance between the wiring to the gate and the output signal line, 1
6 is a load resistance. jiij work is general storage 41゛i
Do it in the same way as the -1-sensor of the mold. FIG. 4 shows the gate pulse φG, noise, and optical signal. In the figure, A is the feedthrough of the Kate pulse due to the line capacity 'Nl''15,
The surface 1 question and answer amount 15 and the load resistance 16 form a differential circuit of the form Jjy,
Therefore, it is in the form of a differential pulse. f3 is times 4'-
Noise IQ due to feedthrough due to IK tunnel capacitance 14
The difference in constant is due to the difference in capacitance size.
ICの作p方によって容h4−は異るため−jけに′電
極間容量14よシも配線間容量の方がかなり太きい。Since the capacitance h4- differs depending on how the IC is manufactured, the inter-wiring capacitance is considerably larger than the inter-electrode capacitance 14.
Cは光信号を表わしている。第3図における出力電圧V
oαtはA、B、Cを合ノ規し/ζイ)のとなる。蓄桓
型の信号は電荷量で見るのが妥尚であシ、雑音電荷の大
部分は線間容量によるものとなっている。C represents an optical signal. Output voltage V in Figure 3
oαt is the sum of A, B, and C/ζa). It is reasonable to view a storage type signal in terms of the amount of charge, and most of the noise charge is due to line capacitance.
光イを号と頼1音の大きさを比較すると、この神のセン
サでけイ″11.音の方が大きいことが多い。例えはフ
ァクンミリ用の密着型リニアイメージセンサに多数の1
6bitアナログマルチプレクサICを使ってスイッチ
ングを行った例では、雑音の平均が光信号の約10倍の
大きさで、しかもばらつきが明状態の光信号と同程度で
あった。2次元のMO8型七ンセンサ合状況は更にきび
しく、スイッチング雑音に対し未対策のものでは雑音が
信号の10’倍にも達すると言われている。今後この釉
の微小信号のスイッチングにアナログマルチプレクサ■
Cが応用されていく上で上記雑音を低減することは非常
に重安な問題である。Comparing the loudness of the sound of the light and the sound of the god sensor, the sound is often louder.
In an example in which switching was performed using a 6-bit analog multiplexer IC, the average noise was about 10 times as large as the optical signal, and the variation was about the same as that of the optical signal in the bright state. The situation with a two-dimensional MO8-type seven-sensor sensor is even more severe, and it is said that if no countermeasures are taken against switching noise, the noise can reach 10' times the signal. In the future, an analog multiplexer will be used for switching the minute signals of this glaze.
Reducing the above-mentioned noise is a very serious problem in the application of C.
本発明の目的は、従来型アナログマルチプレクサICの
欠点を除去せしめ、従来型のICに比べ作製プロセスを
増すことなく高S/N比のアナログマルチプレクサIC
を提供することにある。It is an object of the present invention to eliminate the drawbacks of conventional analog multiplexer ICs, and to provide an analog multiplexer IC with a high S/N ratio without increasing the manufacturing process compared to conventional ICs.
Our goal is to provide the following.
本発明は、該アナログマルチプレクサICにおいてアナ
ログスイッチの入力端のボンディングパノドの位置をチ
ップの周辺から児て出力信号線よ夕も内側に置くことに
より、アナログスイッチの入力端とICのピントの間の
ボンディング配Aj+’が出力信号給の上を越して行な
われ該駆動回路からアナログスイッチに至る配線と出力
信号線が交、←しないことを特徴としている。、
従来型の構成を示す第2図に列する本発明の4目成を第
5図に示す。構成要素自体は゛従来型のものと伺ら変わ
るところはない。本発明のアナログマルチプレクサIC
では第5図から明らかなように、ボンディングワイヤが
出力(ii’i号廠r傍だいでいるため駆動部3から各
アナログスイッチ用L” E Tのゲートに至る開−と
出力信号ツヤ″4とか全く交−a、:l−、ない。この
ため、ボンディングワイヤと出カイ8号線との間の容量
は、層間絶縁膜によって多層配穀によって生ずる線間容
」iに比べてなるかに小びいij+1となる。従って従
来型で9.られたよりな雑音に寄与する容量成分が、F
g T自体の′i11、極問答量しt別として、全く
存在しない。11j述したように線間容量の方がPET
の電極間容量よりもかなり大きく本発明によって雑音の
大部分クニ増除くことかi丁能である。従来のアナログ
マルチプレクサICの中にし[、駆動回路の中を長々と
出力信号線が引回されているものもあり、このような1
cでは駆動回rii中のFE Tのスイッチングノイズ
をも出力に乗せてし才うことになる。これは微小信号を
マルチプレクスするという用途を考えていないためで、
これから増大するこの種の用途に対しては全く役にたた
ないものとなっている。これらのICに比べれば本発明
は微小信号に対し絶大な効果がある。In the analog multiplexer IC, the bonding panoply of the input end of the analog switch is placed from the periphery of the chip to the inside of the output signal line, so that the input end of the analog switch and the focus of the IC The bonding wiring Aj+' is performed over the output signal supply, and the wiring from the drive circuit to the analog switch and the output signal line do not intersect. FIG. 5 shows a four-piece structure of the present invention, which is similar to FIG. 2 which shows the conventional structure. The components themselves are the same as the conventional ones. Analog multiplexer IC of the present invention
As is clear from Fig. 5, since the bonding wire is located near the output (II'i factory), the opening from the drive section 3 to the gate of each analog switch L"ET and the output signal gloss "4" Therefore, the capacitance between the bonding wire and output line 8 is much smaller than the line capacitance 'i' caused by multi-layered grain distribution due to the interlayer insulating film. Therefore, the capacitance component that contributes to the higher noise caused by the conventional type is F
g Except for 'i11 of T itself and the amount of questions and answers, it does not exist at all. 11j As mentioned above, the line capacitance is higher than that of PET.
It is possible to eliminate most of the noise by the present invention, which is considerably larger than the interelectrode capacitance. Some conventional analog multiplexer ICs have long output signal lines routed through the drive circuit;
In c, the switching noise of the FET in the drive circuit rii is also added to the output. This is because the application of multiplexing small signals is not considered.
It is completely useless for this type of use, which will increase in the future. Compared to these ICs, the present invention has a tremendous effect on small signals.
本発明のアナログマルチプレクサICの実施例の一例を
第6図に示す。構成要素は第1図に示したものと全く同
じである。従って、本発明を実施することによるプロセ
スの増加あるいは部品の増加は全くない。この場合駆動
回路3がらアナログスイッチ2に至る配線は、2つに分
れたアナログスイッチアレイの間を通して容易に行なわ
れ、出力信号線4とは全く交差しない。また、ボンディ
ングパノドも、出力信号線が通るだけ内側に寄るi5け
であるからボンディングに対する問題もほとんどない。An example of an embodiment of the analog multiplexer IC of the present invention is shown in FIG. The components are exactly the same as shown in FIG. Therefore, there is no increase in process or number of parts by implementing the present invention. In this case, the wiring from the drive circuit 3 to the analog switch 2 is easily routed between the two divided analog switch arrays, and does not cross the output signal line 4 at all. Furthermore, since the bonding panode is only i5, which is located as far inward as the output signal line passes, there is almost no problem with bonding.
以上の説明で明らかなように、本発明によれは製造プロ
セスをなんらユ1□Mやすことなく、昭iS/N比を有
するアナログマルチプレクサICが得られる。As is clear from the above description, according to the present invention, an analog multiplexer IC having a S/N ratio of Sho i can be obtained without making any changes to the manufacturing process.
第1図は従来型のアナログマルチプレクサICの構成要
素の配置図、第2図り従来型のアナログマルチプレクサ
ICの構成戦素の位f1〜1ン1係を説明するための図
、第3図はリニアセンサに従来型のアナログマルチプレ
クサリ゛を応用L7/(等価回路例を示し、第4同は第
3図の回路における111号波形、第5図は本発明のア
ナログマルチプレクサ1. Cの構成要素の位置lit
係を説明するだめの図、第6図は本発明の実施例の一例
を示す配Ih図である。
図において
1・・・シリコンチップ 2・・アナログスイッチ部
3・・駆動回路部 4・・・出力信号ボTτ5・
・ボンディングパノド 6・・・ボンティングワイヤ7
・・・ICのピン 8・・・F r(T9・・・
線間芥fi:j’ 10・・市 諒]1・・
ホオトダイオード
12・・アナログマルチプレクザIC
\−−−−、ノ′
g 4 図Fig. 1 is a layout diagram of the components of a conventional analog multiplexer IC, Fig. 2 is a diagram for explaining the components of the conventional analog multiplexer IC, and Fig. 3 is a diagram for explaining the components of the conventional analog multiplexer IC. Application of a conventional analog multiplexer to the sensor L7/ position lit
FIG. 6 is a diagram showing an example of an embodiment of the present invention. In the figure, 1... Silicon chip 2... Analog switch section 3... Drive circuit section 4... Output signal button Tτ5.
・Bonding panode 6...Bonting wire 7
...IC pin 8...Fr (T9...
Between the lines fi: j' 10... City Ryo] 1...
Photodiode 12...Analog multiplexer IC \----,ノ'g 4 Figure
Claims (1)
なるアナログマルチプレクサICであって、前記側々の
アナログスイッチの入力端とICのビンとの間のボンデ
ィング配線が出力信号線の上を越して行なわれてなり、
かつ前記駆動回路からアナログスイッチに至る配線が出
力信号線と交差しないように配線されていることを特徴
とするアナログマルチプレクサIC。An analog multiplexer IC consisting of an analog switch array and a drive circuit for driving the same, in which bonding wiring between the input terminals of the analog switches on each side and the bin of the IC is performed over the output signal line. Become,
An analog multiplexer IC characterized in that the wiring from the drive circuit to the analog switch is arranged so as not to intersect with the output signal line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58000316A JPS59125653A (en) | 1983-01-05 | 1983-01-05 | Analog multiplexer ic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58000316A JPS59125653A (en) | 1983-01-05 | 1983-01-05 | Analog multiplexer ic |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59125653A true JPS59125653A (en) | 1984-07-20 |
Family
ID=11470497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58000316A Pending JPS59125653A (en) | 1983-01-05 | 1983-01-05 | Analog multiplexer ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59125653A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
JP2007092779A (en) * | 2005-09-27 | 2007-04-12 | Uchiyama Mfg Corp | Seal member |
JP2008011561A (en) * | 2007-08-23 | 2008-01-17 | Renesas Technology Corp | Semiconductor integrated circuit device |
JP2008038956A (en) * | 2006-08-02 | 2008-02-21 | Jtekt Corp | Sealing device |
-
1983
- 1983-01-05 JP JP58000316A patent/JPS59125653A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
US6331466B1 (en) | 1994-02-21 | 2001-12-18 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
JP2007092779A (en) * | 2005-09-27 | 2007-04-12 | Uchiyama Mfg Corp | Seal member |
JP2008038956A (en) * | 2006-08-02 | 2008-02-21 | Jtekt Corp | Sealing device |
JP2008011561A (en) * | 2007-08-23 | 2008-01-17 | Renesas Technology Corp | Semiconductor integrated circuit device |
JP4711442B2 (en) * | 2007-08-23 | 2011-06-29 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
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