KR100421120B1 - Method for arranging a pixel array in a cmos image sensor - Google Patents

Abstract

The present invention relates to a continuous array of unit pixels of an image sensor comprising at least one photo diode, a reset transistor, a source follower circuit, and one direction of the array. A row decoder positioned at an end and assigned an address in a row direction, at least one first signal control wiring connected to a gate of a selection transistor of each unit pixel driven by the row decoder, At least one second signal control wire connected to the gate electrode of the reset transistor of the respective unit pixels in the same direction as the first signal control wire, a column decoder positioned at the end of the pixel array in a vertical direction to the raw decoder and each unit in the vertical direction At least one driving power voltage wiring supplied to the power of the pixels, and A pixel array method of a CMOS image sensor comprising at least one data output line formed in the same direction as a power supply voltage line, wherein at least one of the first signal control line and the second signal control line is at least on the same axis of the array. And separating the signal at one point of the signal and supplying the signal to the separated wiring at the furnace decoder side in the opposite direction of each of the separated wirings. According to the present invention, a quick control operation of the CMOS image sensor is possible, and the effects of reducing power consumption and reducing noise occurrence frequency due to the reduction of the data line length can be simultaneously obtained.

Description

METHODS FOR ARRANGING A PIXEL ARRAY IN A CMOS IMAGE SENSOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel array arrangement technique of a CMOS image sensor, and more particularly, to a pixel array arrangement method of a CMOS image sensor that realizes high integration and high speed.

A CMOS image sensor is a device that converts an optical image into an electrical signal using a CMOS fabrication technology, and employs a switching method in which MOS transistors are made by the number of pixels and the outputs are sequentially detected using the same. Compared to the CCD (Charge Coupled Device) image sensor, which is widely used as an image sensor, CMOS image sensor has a simple driving method, various scanning methods can be implemented, and signal processing circuit can be integrated on a single chip, thereby miniaturizing the product. In addition, the use of compatible CMOS technology can reduce manufacturing costs and greatly reduce power consumption.

1 is a unit pixel circuit diagram of a CMOS image sensor having a general 3-T structure among such CMOS image sensors.

As shown in FIG. 1, a unit pixel of a CMOS image sensor is composed of one PD (Photo Diode) and four NMOS transistors. The four NMOS transistors change the current of the source follower circuit consisting of Dx, Sel, and DC gate according to the Rx (Reset Transistor), which resets the PD's potential, and the PD's electrode voltage. Dx (Drive Transistor) to change, Sel (selection) which is a transistor to select a row address of the pixel array, and DC gate, which is a load transistor that flows only a constant current by always applying a gate voltage of the transistor at a constant voltage. It is composed.

Here, Vcc represents a driving power supply voltage, Vss represents a ground voltage, and output represents an output terminal of a unit pixel.

That is, as shown in FIG. 1, the unit pixel of the CMOS image sensor is composed of a PD, a transistor for resetting it, and three source follower circuits. The Rx resets the PD to the Vcc power supply and illuminates the reset PD. When electrons and holes are formed in the junction region of the PD, holes diffuse into the silicon substrate and electrons accumulate in the junction region, and the accumulated charge is applied to the Dx transistor gate electrode of the source follower circuit to turn on the Dx transistor. When the selection transistor Sel is selected, an output voltage of a unit pixel is generated according to the voltage change of the PD electrode to output the information of the pixel analogly.

2 is a view for explaining a unit pixel arrangement method of such a CMOS image sensor.

As shown in FIG. 2, a row decoder for specifying a row address around a pixel array, a gate signal control driver of a selection transistor of a pixel, and a gate of a reset transistor of a pixel using the row decoder An electrode signal control driver is disposed in one direction of the array, and at a right angle, a data output of the pixel is connected, and a column decoder to designate column addresses of the pixels and a sensing circuit to amplify the output data are arranged.

This arrangement method increases the time constant because the resistance and capacitance increase as the degree of integration associated with reset, selection, and output signals increases, making it difficult to implement high integration and high speed.

That is, as shown in FIG. 2, the pixel array of a conventional CMOS image sensor is an array of continuous unit pixels composed of one block when the integration degree is low. As the integration degree increases, the array length of the unit pixels increases. This results in increased parasitic resistance and parasitic capacitance, which naturally results in longer time delays for the control signals.

On the other hand, due to the high integration of the sensor product, due to the problem of unit pixels being regularly arranged in both directions of XY due to the limitation of the characteristics of the optical imaging device, a different arrangement method is required than the cell array arrangement method used in the conventional memory device. have.

That is, in the conventional memory device, the physical and electrical positions of the unit cells may be different from each other, and cell arrays may be spaced apart from each other at regular intervals. The physical and electrical positions of must be unified to the physical position, and also must be contiguous between the pixel arrays, thereby limiting the high integration. That is, in the case of the CMOS image sensor, the pixel array should be arranged continuously for each pixel position. If the arrangement is discontinuous in the middle, the image appears discontinuously at the position.

Therefore, unlike conventional memory products, since pixel arrays cannot be spatially separated and placed, there are many constraints on high integration. In the unit pixel arrangement method of the prior art, the time constant of the resistance / capacitance of the control signals is maintained as it is. There has been a demand for a method of arranging pixel arrays that can increase the density and speed up the integration.

Accordingly, the present invention has been made in accordance with the above-described requirements, and by arranging the decoder and the sensing circuit in a symmetrical manner and separating the array of pixels for each bank, the time constant of the resistance * capacitance of the control signals is maintained as it is. It is an object of the present invention to provide a pixel array arrangement method of a CMOS image sensor that eliminates discontinuity and realizes high integration and high speed.

In order to achieve this object, the present invention provides a continuous array of unit pixels of an image sensor composed of at least one photodiode, a reset transistor, and a source follower circuit, and a low-direction address located at one end of the array. And a reset decoder of each of the unit pixels in the same direction as the first signal control wiring and the first signal control wiring connected to the gate of the selection transistor of the respective unit pixels driven by the low decoder. At least one second signal control wiring connected to the gate electrode, a column decoder positioned at the end of the pixel array in the vertical direction with the low decoder, and at least one driving power voltage wiring supplied with the power of each unit pixel in the vertical direction, and driving In the same direction as the power supply voltage wiring A pixel array method of a CMOS image sensor composed of at least one data output wiring, comprising: separating at least one of the first signal control wiring and the second signal control wiring at at least one point on the same axis of the array And supplying a signal to the separated wiring on the side of the row decoder positioned in the opposite direction of each of the separated wirings.

1 is a unit pixel circuit diagram of a general 3-T CMOS image sensor;

2 is a layout view of a pixel array of a conventional CMOS image sensor;

3 is a layout view of a pixel array of a CMOS image sensor according to an exemplary embodiment of the present disclosure;

4 is a discontinuous layout of the selection and reset lines in the bank intermediate position of FIG. 3;

5 is a layout view of a pixel array of a CMOS image sensor according to another exemplary embodiment of the present disclosure;

6 is a discontinuous layout of the selection and reset lines in the bank intermediate position of FIG.

<Explanation of symbols for the main parts of the drawings>

PD: Photodiode

Rx: reset transistor

Dx: Driver Transistor

Sel: Selection Transistor

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a diagram illustrating a pixel array arrangement of a two bank CMOS image sensor according to an exemplary embodiment of the present invention.

Prior to description, FIG. 3 applies the unit pixel of the 3-T structure of FIG. 1 as described above, and thus description of overlapping drawings will be omitted.

As shown in FIG. 3, the method of arranging a pixel array of a CMOS image sensor according to an exemplary embodiment of the present invention provides a pixel array of 2 so that the integration can be doubled while maintaining the same time constant as that of the conventional technology for each pixel control signal. The row decoder, column decoder, and sensing circuit were separated into four bank units. That is, the control signals are separated from each other in two block units, and the data of two columns are output and sensed for one raw decoder address while maintaining the time constant of the control signal. It is to realize the speed of the ship.

FIG. 4 is a diagram illustrating discontinuity results in a bank boundary region for two control signals (reset and selection) for a low decoder direction in the two pixel array banks of FIG. 3. For convenience of description, the number of pixels is one bank. It consists of n and m furnaces and columns, respectively, and the total number of furnaces and columns for both banks is n and 2m. That is, two outputs are generated for each bank for one row address, thereby achieving twice the density and twice the speed.

In this figure, the image of the circled area is enlarged at an intermediate position with respect to the direction of the furnace to show discontinuities in the boundary regions for the two control signals. The physical discontinuities for the signals of the pixel array are discontinuous in the image. It does not appear, doubling the density and doubling the output of the data while keeping the time constants for both control signals the same.

FIG. 5 illustrates another embodiment of the present invention, in which four row decoders, four column decoders, and sensing circuits are arranged to separate control signals, Vcc, and data output signals from each bank in an intermediate position. It is a pixel arrangement method that allows four data to be output to one same raw address while maintaining the time constant of the control signal as in the conventional technology.

By this arrangement method, 4 times density and 4 times speed can be realized.

FIG. 6 shows an example of physically discontinuous arrangement for pixel control signals and Vcc and data output signals, respectively, at bank-level intermediate positions of the pixel array for the embodiment of FIG. 5.

As shown in Fig. 6, two resets connected in the row direction in each bank boundary region of the circularly indicated region, discontinuities for the selection signal and Vcc in the column direction and discontinuities of the data output lines are enlarged. In this case, since there is no effect on signal delay, it is not necessary to discontinuously arrange the lines for Vcc, but it may be advantageous to separate them in terms of reducing power noise.

Hereinafter, a method of arranging a pixel array of a CMOS image sensor according to the present invention will be described in more detail with reference to FIG. 5.

In FIG. 5, the control signals, the column decoders, and the sensing circuits output from the low decoder are operated in the same manner as the conventional bank 0, that is, only one bank in four banks, that is, four banks. Thus, the operation of an image sensor having four times the density while maintaining the same operating speed is possible. In the case of disposing a conventional circuit having the same degree of integration in the method of the present invention, the control signal output from the low decoder is reduced in half compared to the conventional method, thereby enabling a faster control operation and at the same time the length of the data line. The half reduction effect can reduce power consumption and at the same time enable fast operation.

On the other hand, in the case where fast data sensing operation is not required in relation to peripheral circuits, these operations do not operate all banks at the same time, but operate bank 0 and bank 1 simultaneously and put bank 2 and bank 3 in a standby state. In this case, due to the effect of reducing the length of the data line involved in the sensing operation, the operation speed is increased while reducing the frequency of power consumption and noise.

In addition, in the order of decoding and selecting the furnace, the present embodiment is implemented so as to be selected outward from the middle part in comparison with the conventional method in which the operation is performed in a sequentially increasing direction starting from one side of the cell array. Can be.

The arrows shown in FIG. 5 indicate an increasing direction of the addresses, which are related to the selection order of unit pixels at the same time. In the case of banks 0 and 1, the unit pixels are sequentially selected starting from the middle of the entire pixel array and starting from the middle. In the case of banks 2 and 3, the unit pixels are sequentially selected and operated starting from the middle of the entire pixel array and going to the bottom. These operations are preferably performed when each of the unit pixels are operating up or down in the middle part when four banks are operated at the same time, and banks 0 and 1 operate and banks 2 and 3 are in a standby state, or banks 2 and 3 operate. In this case, when banks 0 and 1 are in the standby state, they are preferably operated alternately. When they operate alternately, noise can be reduced due to the effect of increasing the access time between adjacent unit pixels.

Although the present invention has been described in detail based on embodiments, the present invention is not limited to these embodiments, and various modifications, for example, a low decoder or a column decoder and sensing without departing from the gist thereof. Instead of placing the relevant circuitry on both sides of the cell array, use another transmission line to access the pixel array located on one side of the pixel array and not located adjacent to the raw decoder or column decoder and the sensing related circuitry. Pick-up is also possible. In the processing of logic devices, it is common to use a large number of transmission lines, for example, two to five metal lines, in which two or more primary transmission lines are connected to a plurality of unit pixels, and another secondary transmission line is used. In addition, when these primary transmission lines and secondary transmission lines are connected, much of what is intended in the present invention may be obtained. Referring to Fig. 5, for banks 0 and 1, the decoding apparatus for accessing them is a row decoder adjacent to bank 0 (i.e., there is no row decoder adjacent to bank 1), and above the pixel array of bank 0. The first transmission line and the second transmission line are located, and the first transmission line is located in the bank 1 so that in the access operation of the bank 1, the signal of the raw decoder adjacent to the bank 0 is passed through the first transmission line over the pixel array of the bank 0. Is to be passed to 2.

As described above, the present invention enables a quick control operation of the CMOS image sensor, and at the same time, the effects of reducing power consumption and reducing noise occurrence frequency due to the reduction of the data line length can be obtained.

Claims (8)

A continuous array of unit pixels of an image sensor composed of at least one photodiode, a reset transistor, and a source follower circuit, and a row-oriented address located at one end of the array. At least one first signal control wire connected to a gate of a selection transistor of each unit pixel driven by the low decoder, and each unit pixel in the same direction as the first signal control wire. At least one second signal control wiring connected to a gate electrode of a reset transistor of the plurality of transistors, a column decoder positioned at an end of the pixel array in a vertical direction with the row decoder, and at least one drive supplied to a power source of each unit pixel in the vertical direction A power supply voltage wiring and the driving power supply voltage In at least one or more data output to a pixel array method of the CMOS image sensor consisting of wiring lines formed in the same direction, Separating at least one or more of the first signal control wiring and the second signal control wiring at at least one point on the same axis of the array; Supplying a signal to the separated wiring at the row decoder side opposite to the separated wiring; Pixel array arrangement method of a CMOS image sensor comprising a. The method of claim 1, The pixel array arrangement method, Separating at least one of the drive power voltage wires and the data output wires from at least one point in the array; Supplying a signal to the separated wiring at the column decoder side opposite to the separated wiring; The method of claim 1, further comprising the pixel array of the CMOS image sensor. The method of claim 1, The at least one of the first signal control wiring, the second signal control wiring, and the data output wiring is picked up by a metal wiring and connected in the same direction as the picked-up wiring. Pixel array placement method. The method of claim 3, wherein At least one or more of the first and second signal control wires and the data output wires may include a plurality of first and second transmission lines electrically connected to the same pixel control means or data sensing means. 1. A pixel array arrangement method of a CMOS image sensor, wherein a plurality of CMOS image sensor pixel units are connected to a transmission line. The method of claim 1, The unit pixel has a square shape, and the pixel array is composed of a plurality of unit pixels separated from at least one of the first and second signal control wires and the data output wires, and formed on the same silicon. And the pixel array of the configured CMOS image sensor has a square shape. The method of claim 5, wherein The ratio of the short side to the long side of the pixel array is 1: 1 or 1: 2 pixel array method of the CMOS image sensor. The method of claim 2, And the data output lines are separated at least at any one point on the same axis, and a row select signal connected to two or more photodiodes is selected at the same time. The method of claim 2, The data output line is separated at least at any one point on the same axis, and when the low selection signal is generated in the first pixel array in the first and second pixel arrays separated about the data output line, And the data output wires of the second pixel array maintain a standby state.