JPS59125119A - Generating circuit of timing signal - Google Patents

Abstract

PURPOSE:To reduce the occupied area for a generating circuit of timing signals by using a regulator circuit which supplies the bias current to a logical circuit in order to generate the timing signal synchronously with a main clock signal. CONSTITUTION:A resistance 2 and a Josephson element 4 connected in series are connected in parallel to a regulator circuit 1 which shapes the waveform of an AC current is supplied from outside. A control line 3 is put between the circuit and the earth, and the element 4 is controlled with a current Ij flowing to the circuit 1. Then a timing signal synchronous with a main clock signal is generated at a joint 5 between the resistance 2 and the element 4. This timing signal is supplied to a logical circuit. Thus the constitution is extremely simplified for a timing signal generating circuit with a big reduction of the occupied area.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a timing signal generation circuit using a Josephson element, and particularly to a timing signal generation circuit that generates a timing signal synchronized with a clock signal at an arbitrary time in the first half of a duty cycle. The present invention relates to a timing signal generation circuit.

Prior Art and Problems In recent years, research and development of various circuits using Josephson elements has been active.

Naturally, such circuits must be integrated, but for example, in logic circuits using Josephson elements, the timing signals necessary to operate them must be supplied externally. That's what I do.

Therefore, in order to put a logic circuit using Josephson elements into practical use, it is necessary to realize a timing signal generation circuit using Josephson elements and to be able to integrate them into one.

In general, timing signal generating means can be broadly classified into synchronous type and asynchronous type. As a synchronous type, it is possible to adopt a multiphase clock system, but
This poses a problem in terms of occupied area and operating margin, and in the case of an asynchronous type, as the number of bits increases, a complicated circuit is required, resulting in problems in terms of a reduction in calculation speed and an increase in occupied area.

Even in the case of a timing signal generation circuit using a Josephson element, in order to be suitable for integration, it must not be vaguely designed, and after taking into account the above matters,
One must try to obtain something compact with a small footprint.

OBJECTS OF THE INVENTION The present invention provides a timing signal that has a simple configuration and occupies a small area, which can generate a timing signal in synchronization with a main clock signal by using a regulator circuit that supplies a bias current to a logic circuit. The purpose is to provide a generation circuit.

Structure of the Invention In this technical field, that is, in logic circuits using Josephson elements, alternating current supplied from the outside is waveform-shaped using a series connection of a plurality of Josephson elements, and a constant current is applied to a logic circuit network. A regulator circuit of a type that supplies a bias current of 1 is known.

In the present invention, a control line is inserted between a series connection body (regulator circuit) of a plurality of Josephson elements and ground,
A series-connected resistor and a Josephson element are connected in parallel to the series-connected leg j-rake circuit and a control line,
The Josephson element is controlled by the current of the regulator circuit flowing through the control line, and a main clock signal is applied to the connection point between the resistor and the Josephson element at any time in the first half of the duty time of the clock time. This allows it to generate a timing signal synchronized with the logic circuit and send it to the logic circuitry.

Examples of the invention FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention.

In the figure, 1 is a series connection of the waveform shaping Josephson elements (hereinafter referred to as a regulator circuit).
, 2 is a current supply resistor, 3 is a control line for the quantum interference device, 4 is a quantum interference device (the actual device is, of course, a Josephson device, but the above terminology is used for ease of identification), 5
is an output line that is connected to the quantum interference element 4 and propagates an input signal to the next stage element that requires a timing signal, Ts is an alternating current input from the outside, Ij is a current (control) current flowing through the regulator circuit 1) , TI indicates a current flowing through a load (logic circuit network) connected in parallel to the regulator circuit 1, and Ig indicates a gate current flowing through the quantum interference element 4, respectively.

The operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 to 4.

In Figure 2, the vertical axis represents the current (1) in regulator circuit 1.
is a diagram in which the horizontal axis represents voltage (V).

The figure shows the I-■ characteristic of the regulator circuit 1, and also shows what kind of current is shunted to the regulator circuit 1 and the load when an AC voltage Is is applied, and the solid line 6 is A load straight line of a load connected to the regulator circuit 1 is shown. As can be seen from the figure, a conduction current initially flows through the regulator circuit 1, and the voltage V is zero, but when the current exceeds To, the zero voltage state jumps to a finite voltage state, and then This is similar to when a current is passed through a closed resistor, and the regulator circuit 1 performs a regulation operation using such current/voltage characteristics.

FIG. 3 is a diagram in which the vertical axis represents the alternating current Is and the control current Tj, and the horizontal axis represents the time T.

In the figure, the dotted line represents the alternating current Is, the solid line represents the current 1j flowing through the regulator circuit, and the gate current 1g of the quantum interference element 4 is proportional to (Is-Tj).

In the figure, (TI To) is one clock time Tcl
The duty time will be in the middle.

In Figure 4, the vertical axis represents the gate current tg, and the horizontal axis represents the control current 1j.
This is a line diagram taken.

In the figure, changes occurring between To and TI in the gate current 1g and control current Tj of the quantum interference device 4, which are known from FIG. 3, are expressed as threshold current I tl+ (I g
).

After time To, the gate current 1g reaches a constant value, and only the control current Tj changes along the curve shown by the solid line in FIG. In Fig. 4, point A indicates the position of (Ig, Ij) at time T=To, and point C indicates the position of (Ig, Ij) at time T=T.
The positions of (rg, Tj) at cl/2 are shown, but as shown in the figure, if the dark value line 7 is crossed from point C to point C, the quantum interference element 4 switches to a non-zero voltage state, producing an output signal on output line 5.

Since the dark value current 1th (Ig), which is a parameter in FIG. 4, is exactly constant for each clock, as is clear from FIG. A signal is generated. Since 1th (Ig) can be set to an appropriate value by changing the sensitivity of the quantum interference element 4 to the control current 1j, the time Tm at which the timing signal is generated can be changed from To to Tel/
It can be set to any time between 2 and 3. The dark value current 1 th (l g ) shown in FIG. 4 corresponds to the symmetric three-junction interference element, but the dark value current 1 th (f
A better operating margin can be obtained by using a device with a smaller dependence of g) on the gate current rg, such as an asymmetric quantum interference device.

FIG. 5 is a circuit diagram of a main part of another embodiment, and the same parts as those explained in connection with FIG. 162 are indicated by the same symbols.

In the figure, 8 is a control line, 9 and 10 are quantum interference elements,
Itl and lt2 indicate the output currents of the quantum interference elements 9 and 10, respectively. Note that in this example, two quantum interference devices are used to generate timing signals, but
This number may be further increased.

FIG. 6 is a timing chart for explaining the operation of the embodiment shown in FIG. 5. Next, the operation will be explained with reference to this timing chart.

In the embodiment shown in FIG. 5, the quantum interference elements 9 and 10 have different sensitivities to the control current 1j flowing through the control line 8. Therefore, the lines shown in FIG. 6 represent waveforms when the quantum interference elements 9 and 10 are operated in the non-lasoding mode.

FIG. 7 is a main circuit diagram showing still another embodiment.

In the figure, 11 is a quantum interference element, 12 is a control line, and 13 is a quantum interference element.
denotes a power supply line, 14 and 14' resistors, and 15 a control line.

In this embodiment, as a control line, in addition to the control line 12 through which the current from the regulator circuit flows, another control line 15 is provided via a resistor 14 from a power supply line 13 to the logic circuit.

FIG. 8 shows the gate current 1 for the embodiment seen in FIG.
FIG. 3 is a diagram showing the relationship between g and control current 1c.

In the embodiment of FIG. 7, the time of FIG. 3].

Therefore, the value of the off-state current 1off can be set by changing the value of the resistor 14, and therefore,
Setting the time at which the timing signal occurs can be done more easily than relying on the means for adjusting the sensitivity of the quantum interference device described in the embodiment of FIG.

Effects of the Invention According to the present invention, in order to supply a constant bias current to a logic circuit composed of Josephson elements, there is provided a series connection body of a plurality of Josephson elements that shapes the waveform of an externally supplied alternating current; That is, a resistor and a Josephson element connected in series are connected in parallel to the regulator circuit, and the Josephson element is connected in series with the resistor between the series connection body and ground in the regulator circuit. By inserting a control line to control the Josephson element and controlling the Josephson element with the current flowing through the regulator circuit, a timing signal synchronized with the main clock signal is generated at the connection point between the resistor and the Josephson element, and the timing Since the signal is supplied to the logic circuit, the timing signal generating circuit has an extremely simple configuration and is therefore compact, so that its occupied area is extremely small. Also,
The timing signal is the duty ratio of the clock time.
It can be freely adjusted so that it can occur at any time in the first half of time.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a main part of an embodiment of the present invention, Fig. 2 is a diagram showing characteristics of current I versus electric voltage in the embodiment shown in Fig. 1, and Fig. 3 is an alternating current Is and a control current 1j. : Diagram showing characteristics of time T, Figure 4 shows gate current ■g: Control current Ij
5 is a main circuit diagram showing another embodiment of the present invention, FIG. 6 is a timing chart for explaining the operation of the embodiment shown in FIG. 5, and FIG. The figure is a main circuit diagram showing still another embodiment of the present invention, and FIG. 8 is a gate current rg: control current T for the embodiment shown in FIG.
It is a diagram showing the characteristic of c. In the figure, ■ is a series connection of multiple Josephson elements,
2 is the resistance, 3 is the control line, 4 is the quantum interference element, 5 is the output line, Is is the alternating current, Ij is the current flowing through the regulator circuit (control current), ■1 is the current flowing to the load, tg is the gate current be. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 3 Figure 8

Claims (1)

[Claims] a series connection body of a plurality of Josephson elements; a resistor having one terminal connected to one terminal of the series connection body; a Josephson element connected between the other terminal of the resistor and ground; A timing signal generating circuit comprising: a control line connected between the series connection body and ground, and controlling a Josephson element inserted between the other terminal of the resistor and ground.