JPS59125079A - Method for measuring transistor - Google Patents

Method for measuring transistor

Info

Publication number
JPS59125079A
JPS59125079A JP23375182A JP23375182A JPS59125079A JP S59125079 A JPS59125079 A JP S59125079A JP 23375182 A JP23375182 A JP 23375182A JP 23375182 A JP23375182 A JP 23375182A JP S59125079 A JPS59125079 A JP S59125079A
Authority
JP
Japan
Prior art keywords
transistor
base
collector current
fall time
parameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23375182A
Other languages
Japanese (ja)
Other versions
JPS6346381B2 (en
Inventor
Yasutaka Nakatani
中谷 安孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23375182A priority Critical patent/JPS59125079A/en
Publication of JPS59125079A publication Critical patent/JPS59125079A/en
Publication of JPS6346381B2 publication Critical patent/JPS6346381B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2607Circuits therefor
    • G01R31/2608Circuits therefor for testing bipolar transistors
    • G01R31/261Circuits therefor for testing bipolar transistors for measuring break-down voltage or punch through voltage therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To measure easily and non-destructively a reverse bias breakdown rating of a bipolar transistor, and to measure a fall time of a collector current by measuring an S parameter of a bipolar transistor to be tested, and executing an operation. CONSTITUTION:A mean impurity density of a base and depth of the base are varied as parameters, and other all design conditions are not varied but are kept constant, by which plural bipolar transistors are manufactured. An S parameter is measured with respect to each of these bipolar transistors. An absolute value of one element S11 of the S parameter is denoted as rho and an angle acute angleS made by S11 is denoted as theta, by which an input reflection coefficient GAMMA is derived by the expression [ I ]. By using the S parameter, the maximum single direction power gain MSG is derived by the expression [II]. In the same way, by using the S parameter, a stable coefficient K is derived by the expression [III]. By using said MSG and K, the maximum competent power gain MAG is derived by the expression [IV].

Description

【発明の詳細な説明】 (1)  発明の技術分野 本発明は、トランジスタの測定方法に関し、特に/々イ
ポーラトランジスタの逆・々イアス破壊耐量の測定方法
と、コレクタ電流の下降時間の測定方法とに関する。詳
しくは、かかる測定を簡易に、しかも、非破壊的になす
改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for measuring transistors, and in particular, a method for measuring the reverse/polar breakdown strength of a polar polar transistor, and a method for measuring the fall time of a collector current. Regarding. More specifically, the present invention relates to an improvement that makes such measurements simple and non-destructive.

(2)技術の背景 逆バイアス破壊耐量とは、バイポーラトランジスタのコ
レクタ電流をON、 OFF してなす使用方式におい
てバイポーラトランジスタがON ′&態からOFF状
態に移行する際、このバイアi?−ラトランジスタを破
壊に至らしめることなくオリ用しうるコレクタ・エミッ
タ間電圧とコレクタ電流とで定義される。9荷がインダ
クタンスを含むスイッチング回路に使用されるノ々イボ
ーラトランジスタの重要な枠側ファクタの一つである。
(2) Background of the technology Reverse bias breakdown capability refers to the amount by which the bias i? - It is defined by the collector-emitter voltage and collector current that can be used without destroying the transistor. This is one of the important frame-side factors for Nono Ibora transistors used in switching circuits that include inductance.

いうまでもなく、この耐量はなるべく大きいことが望ま
しい。一方、下降時間とは、ノぐイボーラトランジスタ
のベースに印加されている正ノ々イアス電圧を反転させ
てこのノ々イボーラトランジスタをOFFする場合、コ
レクタ電流が下降し、て第1図のB点から0点まで移行
するまでの時間をいう。この時間はなるべく短いことが
望ましい。
Needless to say, it is desirable that this tolerance is as large as possible. On the other hand, the fall time means that when the positive and negative voltages applied to the base of a non-Ibora transistor are reversed to turn off this Non-Ibora transistor, the collector current decreases and as shown in Fig. 1. This is the time it takes to move from point B to point 0. It is desirable that this time be as short as possible.

これらの値を知ることは、ノ々イボーラトランジスタを
使用する回路設計には是非必要なことであり、更に、ノ
々イポーラトランジスタの改良のためにも会費であるか
ら、これらの測定方法は、工業的にも、また、技術開発
の面からも、必須であり、また、極グ・て重要である。
Knowing these values is absolutely necessary for circuit design using Nono Ibora transistors, and furthermore, since it is a membership fee for improving Nono Ibora transistors, these measurement methods are It is essential and extremely important from an industrial and technological development perspective.

(3)  従来技術と間悄点 逆・ζイアス破壊耐Heやコレクタ電流の下降時間の測
定は、従来、第2図に示す如き回路を使用して実験室的
になしていた。図において、1は試験されるノ々イ2−
ラトランジスタであり、そのコレクタ・エミッタ間にt
′、ζ電の2とインダクタンス3とが直列に接続され、
また、そのベースには逆・々イアスミ源4と正方向パ少
ス信号を印加するパルス信号発生器5が接続される。な
お、ダイオード6と電源7とは電圧クランプ回路を構成
する。この回路において、パルス信号発生器5が正方向
パルス信号をトランジスタ1のベースに印加すると、ト
ランジスタlは、以下に述べるようにON −OFFす
る。第3図において、vBはベース電圧を示し、トラン
ジスタ1のベース電位は、ノξルスが印加されない状態
においては負に保持され、パルスの印加されている期間
のみ正に反転する。よりはベース電流であり、ベース電
圧vBの変化にしたがって図示するように変化する。■
。8はコレクタ電流であり、ベース電流よりの正方向流
入とともに州力11シ、その逆方向の流れとともに増加
を停止し、減少し、逆に零に至る。VZaはコレクタ・
エミッタ間低圧であり、コレクタ電流の発生とともに零
となり、その減少に起因する過渡現象を経由して外部電
源によって規定される電圧ま〒上昇する。このとき、ノ
ぐイポーラトランジスタにあっては、イースミ正反転時
にベース冑域(ベース−極とエミッタ領域を接続する電
路であり、ベース電流の電流通路)に抵抗が残留するこ
とが避は難い。この領域特にエミッタ領域の中央部のエ
ミッタ・ベース接合部は逆ノ々イアスになりきれずこの
接合から電荷は注入されつづけ、その電荷に対しインダ
クタンスLより大金な゛幅圧がコレクタエミッタに印7
JIl サれ、その接合は局部的に高熱になり破壊する
。この現象が逆バイアス破壊耐量である。上記の如きI
回路を使用して次第にコレクタ・エミッタ間電流工Cを
助力pさせてトランジス゛りを破壊に−至らし2め、破
壊寸前の電流(第1図A点)を測定していた(゛電圧は
クランプ電圧により、一定の電圧値に保持されている。
(3) Conventional technology and inverse zebra point/ζ ias Breakdown resistance He and collector current fall time have conventionally been measured in a laboratory using a circuit as shown in FIG. In the figure, 1 is the node to be tested 2-
It is a transistor with t between its collector and emitter.
', ζ electric current 2 and inductance 3 are connected in series,
Further, connected to the base thereof are a reverse/parallel Asumi source 4 and a pulse signal generator 5 for applying a forward pass signal. Note that the diode 6 and the power supply 7 constitute a voltage clamp circuit. In this circuit, when the pulse signal generator 5 applies a positive direction pulse signal to the base of the transistor 1, the transistor 1 is turned on and off as described below. In FIG. 3, vB indicates the base voltage, and the base potential of the transistor 1 is held negative when no pulse is applied, and is inverted to positive only during the period when the pulse is applied. This is the base current, which changes as shown in the figure as the base voltage vB changes. ■
. Reference numeral 8 is a collector current, and when the current flows in the forward direction from the base current, the current flows, and when the current flows in the opposite direction, it stops increasing, decreases, and conversely reaches zero. VZa is the collector
The emitter-to-emitter voltage is low and becomes zero with the generation of collector current, and rises to the voltage specified by the external power supply through a transient phenomenon caused by its decrease. At this time, in the case of polar polar transistors, it is unavoidable that resistance remains in the base region (the electrical circuit connecting the base-pole and the emitter region, and the current path for the base current) during positive inversion. . In this region, especially the emitter-base junction in the center of the emitter region, the emitter-base junction cannot completely become an inverse bias, and charge continues to be injected from this junction, and a width pressure greater than the inductance L is applied to the collector-emitter. 7
When JIl is worn out, the joint becomes locally heated and destroyed. This phenomenon is the reverse bias breakdown capability. I as above
Using a circuit, the collector-emitter current controller C was gradually assisted to destroy the transistor, and the current on the verge of destruction (point A in Figure 1) was measured (the voltage was clamped). The voltage is maintained at a constant voltage value.

)。一方、下降時間は、第1図におけるコレクタ電流X
aの下降する時間(第1図B点から0点まで)であり、
上記の叩き回路を使用してなす破壊試験において破壊に
至る寸前の条件のコレクタ電流の下降時間をブラウン管
オツシロスコープ等ヲ使用してこれを測定していた。
). On the other hand, the falling time is the collector current
The time for a to fall (from point B to point 0 in Figure 1) is
In a destructive test using the above-mentioned tapping circuit, the fall time of the collector current under conditions on the verge of destruction was measured using a cathode ray tube oscilloscope or the like.

したがって、従来技術における逆バイアス破壊耐量やコ
レクタ電流の下降時間の測定方法は実験室的であ番)工
業的使用に適さず、操作も必ずしも容易ではなく非能率
的であり個人差も発生しゃすく、改良すべき点を含むも
のであった。特に、逆バイアス破壊耐量の測定は破壊試
験であるため、工朶的利用には極めて不適“であり、看
過し雌い欠点であった。
Therefore, the conventional methods for measuring reverse bias breakdown strength and collector current fall time are laboratory-based, not suitable for industrial use, are not necessarily easy to operate, are inefficient, and are subject to individual differences. , including points that should be improved. In particular, since the measurement of reverse bias breakdown strength is a destructive test, it is extremely unsuitable for industrial use, and this was a drawback that could have been overlooked.

(4)  発明の目的 本発明の目的はこの欠点を解消するものであり、操作が
簡易で非破壊的であり工業的利用に適する等多くの利益
を有する、トランジスタ特に・々イポーラトランジスタ
の逆ノ々イアス破壊itす量の測定方法と、コレクタ電
流の下降時間の測定方法とを提供することにある。
(4) Purpose of the Invention The purpose of the present invention is to eliminate this drawback, and to provide a transistor that has many advantages such as being easy to operate, non-destructive, and suitable for industrial use, especially the reverse of the impolar transistor. It is an object of the present invention to provide a method for measuring the amount of noise breakdown and a method for measuring the fall time of a collector current.

(5)  発明の構成 上記の目的は、ベースの不純物瞬腿とベースの深さとを
パラメータとして変化させて製作された複数のトランジ
スタのそれぞれについてペース抵抗、コレクタ電流の下
降時間及び逆ノ々イアス破壊耐量とを測定し7、ベース
抵抗と逆ノ々イアス破壊耐量との「tj係またはベース
抵抗とコレクタ電流の下降時間との関係を求めておき、
被測定トランジスタのベース抵抗を測定し、前記関係に
よI)、被測定トランジスタの逆ノ々イアス破壊耐量ま
たはコレクタ申;流の下降時間を検出することを特徴と
する、トランジスタにおける逆バイアス破壊耐量及びコ
レクタ電流の下降時間の測定方法と、ベースの不純物f
A厩とペースの深さとをパラメータとして変化させて製
作された複数のトランジスタのそれぞれl二ついて最大
有能電力利得、コレクタ電流の下((革vi 1i−t
j及び逆・ζイアス破壊Mtとを測定し、ル゛大有能゛
16;力利得と逆、Sイアス破壊耐量との関係または最
大有能1;力利得とコレクタ電流の下降時間との関係を
求めておき、被測定トランジスタの最大有能電力利得を
測定し、前記関係により、被測定置 トランジスタの逆バイアス破壊耐量またはコレクタ゛t
に流の下;嘩時間を検出することを特徴とする、トラン
ジスタにおける逆バイアス破壊耐貢及びコレクタ電流の
下降時間の測定方鋳により達成される0 上記の構成に規定されるベース抵抗の?jI++ wと
最大有能電力利得の測定とは下記の如くなされる。
(5) Structure of the Invention The above object is to improve the pace resistance, the fall time of the collector current, and the reverse noise breakdown for each of a plurality of transistors manufactured by changing the impurity concentration of the base and the depth of the base as parameters. 7, find the tj relationship between the base resistance and the reverse negative current breakdown strength, or the relationship between the base resistance and the fall time of the collector current,
Reverse bias breakdown capability of a transistor, characterized by measuring the base resistance of the transistor to be measured, and detecting the reverse bias breakdown capability or collector current fall time of the transistor to be measured according to the above relationship I) and the method of measuring the fall time of the collector current, and the impurity f of the base.
Each of the plurality of transistors fabricated by varying the depth and depth of the pace as parameters has a maximum available power gain, under the collector current ((leather vi 1i-t
J and reverse/ζ ias breakdown Mt are measured, and the relationship between the force gain and the inverse and S ias breakdown withstand capacity or the maximum capacity 1; the relationship between the force gain and the fall time of the collector current is determined. Determine the maximum available power gain of the transistor under test, and from the above relationship, calculate the reverse bias breakdown strength or collector t of the transistor under test.
This is achieved by measuring the reverse bias breakdown resistance and the fall time of the collector current in a transistor, which is characterized by detecting the breakdown time of the base resistance defined in the above configuration. The measurements of jI++w and the maximum available power gain are made as follows.

まず、被験−々イボーラトランジスタが入力周波数に対
して増幅作用を何する範囲のなるべく萬い周波数をもっ
て、Sパラメータ(下記される式をもって示される4要
素の行列)を測定する。
First, the S-parameter (a 4-element matrix expressed by the following formula) is measured at as many frequencies as possible within the range in which the Ibora transistor under test performs an amplification effect on the input frequency.

ところで、allの絶対値1 stt +をρをもって
表わし、sllのなす角/S11をθをもって表わすと
、入力反射係数「は、 r=ρexP (iθ) となり、入力インピーダンスzi は、但し、zoは基
準インピーダンスであり通常(資)〔Ω〕↑ある。
By the way, if the absolute value 1 stt + of all is expressed by ρ, and the angle formed by sll/S11 is expressed by θ, then the input reflection coefficient ``is r=ρexP (iθ), and the input impedance zi is, however, zo is the reference value. It is impedance and is usually (equal) [Ω] ↑.

となり、入力インピーダンスZ1の実数成分R1nは、 zO(l−ρ2) と表わさhる。そして、ベース抵抗rbはおお加入力イ
ンピーダンスの実数成分に等しいから、ベース抵抗は、 として求められる。  − 一方、最大有能電力利得MAGは、 h4AG = MBG (K−1”廼−])であるから
、上記のSノぐラメータから求めることができ、またK
(安定件数)は、 であるから、これも上記のSパラメータから求めること
ができる。
The real component R1n of the input impedance Z1 is expressed as zO(l-ρ2). Since the base resistance rb is equal to the real component of the input impedance, the base resistance can be obtained as follows. - On the other hand, since the maximum available power gain MAG is h4AG = MBG (K-1" -]), it can be found from the above S parameter, and K
(Stable number of cases) is as follows, so this can also be determined from the above S parameter.

本発明は、逆バイアス破壊耐量と、コレクタ電流の下降
時間とがベース抵抗または最大有能電力利得に相関する
という現象な第1」用したものであり、この現象を発見
した過程につき略述する。
The present invention takes advantage of the phenomenon that the reverse bias breakdown capability and the fall time of the collector current are correlated with the base resistance or the maximum available power gain.The process by which this phenomenon was discovered will be briefly described below. .

エミツタ幅とエミッタ本数とを変化させてベース抵抗の
みを変化させ、ベース面積、拡散方法等のウェーハゾロ
セス条件等はすべて同一として複数のトランジスタを試
作し、それぞれについてベース抵抗と、コレクタ電流の
下降時間とを測定した後逆ノぐイアス破壊耐量を測定し
た。そして、ベース抵抗をX軸とし、下降時間と逆バイ
アス破壊耐量とをY軸としてグラフを描き第4図、第5
図を得た。図において、Aは下降時間を表わし、Bは逆
・々イアス破壊耐量を表わす。図よりコレクタ電流の下
降時間、逆バイアス破壊耐量ともベース抵抗と相関する
ことが確認された。
By changing only the base resistance by changing the emitter width and the number of emitters, we prototyped multiple transistors with all the same wafer processing conditions such as base area and diffusion method, and for each transistor, the base resistance and collector current decreased. After measuring the time, the reverse diaphragm fracture resistance was measured. Then, draw a graph with the base resistance as the X axis and the fall time and reverse bias breakdown capacity as the Y axis, as shown in Figures 4 and 5.
I got the diagram. In the figure, A represents the falling time, and B represents the reverse-to-earth destruction resistance. From the figure, it was confirmed that both the fall time of the collector current and the reverse bias breakdown strength are correlated with the base resistance.

次に、上記と同様の複数のトランジスタを試作し、それ
ぞれについて最大有能電力利得とコレクタ電流の下降時
間とを測定した後、逆ノ々イアス破壊耐量を測定した。
Next, a plurality of transistors similar to those described above were prototyped, and after measuring the maximum available power gain and collector current fall time of each transistor, the reverse noise breakdown withstand capacity was measured.

そして、最大有能電力利得(測定周波数は16 MHz
 ?ある。〕をX軸とし、コレクタ電流の下降時間と逆
ノ々イアス破壊耐量とをY軸としてグラフを描き第6図
、第7図を得た。
and the maximum available power gain (measurement frequency is 16 MHz
? be. ] was plotted as the X-axis, and the fall time of the collector current and the inverse noise breakdown capacity were plotted as the Y-axis, and FIGS. 6 and 7 were obtained.

図においてCはコレクタ電流の下降時間でありDは逆ノ
々イアス破壊耐量↑ある0図より、コレクタ電流の下降
時間、逆バイアス破壊耐量とも最大有能電力利得と相関
することが確認された。
In the figure, C is the fall time of the collector current, and D is the reverse bias breakdown withstand capacity ↑ From the figure, it was confirmed that both the collector current fall time and the reverse bias breakdown capacity are correlated with the maximum available power gain.

そして、コレクタ電流の下降時間と逆バイアス破壊耐肴
のいずれも、上記せる如き実験室的方法をもってしか測
定することができず、特に逆/々イアス破壊耐量は破坂
試験であるに反し、ペース抵抗と最大有能電力利得はい
ずれも上記せるとおり、Sパラメータを測定して、これ
にもとづいて簡単な演算を更行すること(ユより容易に
求めることができるから極めて有利である。特に、Sパ
ラメータの測定は非破曖的になしうるから特に有第1」
である。そして、本発明の方法による場合と従来技術の
方法による場合の誤差はro(%)以下であり工業的に
は十分許容される範囲である。
Both the fall time of the collector current and the reverse bias breakdown resistance can only be measured using the laboratory method described above. As mentioned above, both the resistance and the maximum available power gain can be determined more easily by measuring the S-parameter and performing simple calculations based on this, which is extremely advantageous. In particular, This is especially true because the measurement of S-parameters can be done unambiguously.
It is. The error between the method of the present invention and the method of the prior art is less than ro (%), which is within an industrially acceptable range.

以上説明せるとおり、本発明によれば、被験バイポーラ
トランジスタのSノぞラメータを測定して、壊的に、バ
イポーラトランジスタの逆バイアス破壊耐量の測定と、
コレクタ電流の下降時間の測定をなすことができる。
As explained above, according to the present invention, the S-noise parameter of the bipolar transistor under test is measured, and the reverse bias breakdown strength of the bipolar transistor is destructively measured.
A measurement of the fall time of the collector current can be made.

(6)  発明の実施例 以下、本発明の実施例に係る、ノ々イボーラトランジス
タの逆バイアス破壊耐量の測定方法と、コレクタ電流の
下降時間の測定方法との各工程を更に説明する。
(6) Embodiments of the Invention Hereinafter, each step of a method for measuring the reverse bias breakdown strength of a Nono Ibora transistor and a method for measuring the fall time of collector current according to an embodiment of the present invention will be further explained.

(イ)ベースの平均不純物#贋とベースの深さとをパラ
メータとし、て変化させ、その仙すべての設計条件はり
f化させることなく一定に保持して複数のバイポーラト
ランジスタを製造する。
(a) A plurality of bipolar transistors are manufactured by changing the average impurity level of the base and the depth of the base as parameters, and keeping all the design conditions constant without changing them.

(ロ)これらのバイポーラトランジスタのそれぞれζ二
対し、S−ξラメータを測定する。
(b) Measure the S-ξ parameter for each of these bipolar transistors.

e→B ハラメータの1喪素811の絶対値I S、、
 Iをρとし、S11のなす角/Sをθとして、入力反
射係数「を下式により求める。
e→B Absolute value of Harameter's 1st element 811 I S,,
Where I is ρ and the angle /S formed by S11 is θ, the input reflection coefficient ``is determined by the following formula.

「=ρexp (iθ) つづいて、入力反射係数「を使用して、入力インピーダ
ンスz1を下式により求める。
= ρexp (iθ) Next, using the input reflection coefficient, the input impedance z1 is determined by the following formula.

1−[ 入力インピーダンスz1の実数成分C二よっておおむね
代表されるR−ス抵抗rbを下式により求める。
1-[ The R-base resistance rb, which is approximately represented by the real component C2 of the input impedance z1, is determined by the following formula.

に)B 、eラメータを使用して、最大単方向電力利得
MEIGを下式により求める。
B) Using the e parameter, the maximum unidirectional power gain MEIG is determined by the following formula.

同じくSパラメータを使用して安定係数Kを下式によ番
)求める。
Similarly, using the S parameter, the stability coefficient K is determined by the following formula.

MSGとKとを使用して、最大有能電力利得MAGを下
式により求める。
Using MSG and K, the maximum available power gain MAG is determined by the following formula.

MAG=MSG (K −K” −1)(ホ)上記によ
りベース抵抗と最大有能電力利得の決定されたノ々イポ
ーラトランジスタのそれぞれC二従来技術におけるコレ
クタ電流の下降時間と逆・ぐイアス破壊耐量とを測定し
て、fJJ4.5.6.7図に示す如き関係、すなわち
、ペース抵抗とド降時間の関係、ペース抵抗と逆バイア
ス破壊耐量Q)関係、最大有能電力利得とコレクタ電流
の下降時間Q)関係、最大有能電力−利得と逆・々イア
ス破壊耐量の関係を求める。この関係は上記のタライテ
リア(−もとづく/々イボーラトランジスタのいずれl
二もあてはまるはずであり、本実施例に係る逆/々イア
ス破壊耐量と、コレクタ電流の下降時間の測定方法1−
おける基準情報となる。
MAG=MSG (K −K” −1) (E) The fall time of the collector current and the inverse curve in the prior art are Destruction withstand capacity is measured, and the relationship as shown in figure fJJ4.5.6.7 is established, that is, the relationship between pace resistance and drop time, the relationship between pace resistance and reverse bias breakdown capacity Q), and the maximum available power gain and collector Find the relationship between the current fall time Q), the maximum available power-gain, and the reverse/reverse-earth breakdown withstand capacity.This relationship is
2 should also apply, and the measurement method 1- of the reverse/semi-irradiation breakdown withstand capacity and the fall time of the collector current according to the present example.
This will serve as standard information.

(へ)被測定バイポーラトランジスタに対し、上記(イ
)〜に)に述べたと同一の過程によりペース抵抗rbと
最大有能電力利得)4 A Gとを測定する0(ト)上
記(ホ)の工程において用意した基準情報と、被測定ト
ランジスタのペース抵抗r1)及び/又は最大有能電力
利得MAGとを使用して被測定トランジスタの逆ノ々イ
アス破壊耐量と、コレクタ電流(h下降時間とを求める
(f) For the bipolar transistor under test, measure the pace resistance rb and the maximum available power gain (4 A G) using the same process as described in (a) to (b) above. Using the reference information prepared in the process and the pace resistance r1) and/or maximum available power gain MAG of the transistor under test, the reverse noise breakdown withstand capacity and collector current (h fall time) of the transistor under test are calculated. demand.

木実だ6 例において逆・々イアス破壊耐量と、コレク
タ電流の下降時間とを求めた後従来技術における方法を
使用して下降時間と逆・々イアスW壊耐量とを測定して
、本実施例における誤差の程度を確認した。その結果、
本実施例における誤差は10〔匍以下であることが確認
された。
Kinoda 6 In the example, after determining the reverse-to-direction breakdown strength and the fall time of the collector current, the fall time and the reverse-to-direction breakdown strength were measured using the method in the prior art. The degree of error in the example was confirmed. the result,
It was confirmed that the error in this example was less than 10 cm.

(7)発明の詳細 な説明せる七おり、本発明によれば、操作が簡易で非破
壊的であ番)工業的利用に適する等多くの利益を有する
、トランジスタ特にノ々イボーラトランジスタの逆バイ
アス破壊耐量の測定方法とコレクタ電流の下降時間の測
定方法とを提供することができる。
(7) Detailed Description of the Invention According to the present invention, a reverse transistor, especially a non-Ibora transistor, has many advantages such as simple operation, non-destructive operation, suitability for industrial use, etc. A method for measuring bias breakdown strength and a method for measuring fall time of collector current can be provided.

【図面の簡単な説明】 !81図はノζイボーラトランジスタのコレクタ゛風流
特性を表す曲線因、第2図は従来技術における、/々イ
、彼−ラトランジスタの逆バイアス破壊耐量と下降時間
の測定方法に使用される回路の概略接続図であり、第3
図はその動作を説明するタイムチャートである。夷4.
5図はペース抵抗と下降時間の相関、ペース抵抗七逆ノ
々イアス破喚耐惜の相関を示すグラフであり、第6.7
図は最大有能゛磁力利得とコレクタ′献尚の下降時間、
最大讐龍電力利得と逆バイアス破壊耐量の相関を示すグ
ラフである。 1・・・ノ々イポーラトランジスタ、2.4.7・・・
電曽、3・・・インダクタンス、5・・・パルス発振器
、6・・・ダイオード、vB・・・ベース電圧、工n・
・・ベース′屯ωt、xag・・・コレクタ電流、VO
K・・・コレクタ・エミッタ電汗、A、O・・・下降時
間、BSD・・・逆バイアス破7+I4劇量。 第1図 第4図 ぺ−ス才改植山美 ペース抵抗(n) 最大有能電力力j得 粂人為能電力利イ尋
[Brief explanation of the drawing]! Figure 81 shows the curve factor representing the collector wind current characteristics of the ζ Ibora transistor, and Figure 2 shows the circuit used in the prior art to measure the reverse bias breakdown strength and fall time of the Ibora transistor. This is a schematic connection diagram, and the third
The figure is a time chart explaining the operation. Yi 4.
Figure 5 is a graph showing the correlation between pace resistance and descent time, and the correlation between pace resistance and resistance to failure.
The figure shows the maximum effective magnetic force gain and the fall time of the collector,
It is a graph showing the correlation between maximum power gain and reverse bias breakdown capacity. 1... Nono polar transistor, 2.4.7...
Electromagnetic wave, 3... Inductance, 5... Pulse oscillator, 6... Diode, vB... Base voltage, Engineering n.
... Base ωt, xag ... Collector current, VO
K... Collector/emitter electric sweat, A, O... Fall time, BSD... Reverse bias failure 7 + I4 dramatic amount. Fig. 1 Fig. 4 Pace improvement Ueyama beauty Pace resistance (n) Maximum capable electric power

Claims (2)

【特許請求の範囲】[Claims] (1)ベースの不純物濃度とベースの深さとをノξラメ
ータとして変化させて製作された複数のトランジスタの
それぞれについてベース抵抗、コレクタ電流の下降時間
及び逆バイアス破壊耐量とを測定し7、前記ベース抵抗
と逆バイアス破壊耐量との関賃・またはベース抵抗とコ
レクタ電流の下降時1司とのrli1件を求めておき、
被測定トランジスタのペース抵抗を測定して前記関係よ
り、被測定トランジスタの逆バイアス破壊耐量またはコ
レクタ電流の下降時間を検出することを特徴とするトラ
ンジスタの測定方法。
(1) Measure the base resistance, collector current fall time, and reverse bias breakdown strength of each of a plurality of transistors manufactured by varying the base impurity concentration and base depth as a parameter ξ. Find the ratio between the resistance and the reverse bias breakdown capacity, or the rli between the base resistance and the collector current when it falls,
A method for measuring a transistor, comprising: measuring the pace resistance of the transistor to be measured, and detecting the reverse bias breakdown strength or the fall time of the collector current of the transistor to be measured from the above relationship.
(2)ベースの不純物濃度とベースの深さkをパラメー
タとして変化させて製作された複数のトランジスタのそ
れぞれについて最大有能電力利得、コレクタ電流の下降
時間及び逆バイアス破壊耐量とを測定し、最大有能゛重
力利得と逆、6イアス破壊耐量との関係または最大有能
電力利得とコレクタ電流の下降時間との関係を求めてお
き、被測定トランジスタの最大有能電力利得を測定して
前記関係より、被測定トランジスタの逆バイアスim耐
tまたはコレクタ電流の下降時間を検出することを特徴
とするトランジスタの測定方法。
(2) Measure the maximum available power gain, collector current fall time, and reverse bias breakdown capability of each of multiple transistors manufactured by varying the base impurity concentration and base depth k as parameters, and Find the relationship between the available gravity gain and the inverse, 6-year breakdown withstand capacity, or the relationship between the maximum available power gain and the fall time of the collector current, and measure the maximum available power gain of the transistor under test to determine the above relationship. A method for measuring a transistor, which comprises detecting the reverse bias im resistance t or the fall time of the collector current of the transistor to be measured.
JP23375182A 1982-12-29 1982-12-29 Method for measuring transistor Granted JPS59125079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23375182A JPS59125079A (en) 1982-12-29 1982-12-29 Method for measuring transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23375182A JPS59125079A (en) 1982-12-29 1982-12-29 Method for measuring transistor

Publications (2)

Publication Number Publication Date
JPS59125079A true JPS59125079A (en) 1984-07-19
JPS6346381B2 JPS6346381B2 (en) 1988-09-14

Family

ID=16960002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23375182A Granted JPS59125079A (en) 1982-12-29 1982-12-29 Method for measuring transistor

Country Status (1)

Country Link
JP (1) JPS59125079A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6238372A (en) * 1985-08-13 1987-02-19 Mitsubishi Electric Corp Measuring method for transistor
JPS6376007U (en) * 1987-09-26 1988-05-20
WO2002052287A3 (en) * 2000-12-26 2002-12-05 Ericsson Inc Method and device for testing of a transistor using a network analyzer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223381U (en) * 1988-07-29 1990-02-15

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51111078A (en) * 1975-03-26 1976-10-01 Hitachi Ltd Transistor testing device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51111078A (en) * 1975-03-26 1976-10-01 Hitachi Ltd Transistor testing device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6238372A (en) * 1985-08-13 1987-02-19 Mitsubishi Electric Corp Measuring method for transistor
JPS6376007U (en) * 1987-09-26 1988-05-20
JPH0322321Y2 (en) * 1987-09-26 1991-05-15
WO2002052287A3 (en) * 2000-12-26 2002-12-05 Ericsson Inc Method and device for testing of a transistor using a network analyzer

Also Published As

Publication number Publication date
JPS6346381B2 (en) 1988-09-14

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