JPS59123241A - Method of analysis of defective semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable to accurately detect the generation of a defect and the defective point on a semiconductor integrated circuit by a method wherein, when a defect analysis is going to be performed using an EB tester, the information on positions corresponding to a wiring region only are compared with. CONSTITUTION:The constant image obtained by the EB tester 11 is converted by a binary circuit 12, it is memorized in the first image memory 13 as an image information for the LSI of non-defective article, and it is memorized in the second image memory 14 for the LSI on which a defect analysis will be performed. Various kinds of conditions such as a multiplying factor and the like for the EB tester 11 are established in such a manner that the size of a memory block 21, either of the image memories of 13 and 14, will be coincided with the width of the wiring region on the LSI. Image information is read out from each memory block 21 corresponding to said two memories 13 and 14, and the result of comparison made by a comparison circuit 15 is memorized in a memory 16. When the contents of the memory 16 is indicated by an indicator 17 corresponding to the contrast of brightness and darkness, the defective part of the wiring region can be detected instantly.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to an EB tester (EIectron beam
The present invention relates to a failure analysis method for defective semiconductor integrated circuits, and in particular to an improvement that makes it possible to easily perform failure analysis by applying image processing technology.

[Technical background of the invention and its problems]

It is well known that the emission efficiency of secondary electrons generated from the surface of a sample by irradiating the sample with an electron beam changes depending on the surface potential of the sample. In other words, when a sample with a potential distribution is observed with a secondary electron image, a contrast image is obtained in which the surface potential is high (brass) areas are dark and low (minus) areas are bright. is generally called potential contrast. Therefore, by utilizing this phenomenon and observing the entire LSI potential contrast image and knowing the entire internal potential distribution state, it is possible to perform a complete failure analysis of the operation. .

Conventionally, this failure analysis has been performed using the following procedure. First, the voltage fL'iz is observed and recorded in a potential contrast image of a good LSI. This recording method is
Traditionally, photography is the most common method. Next, a potential contrast image is observed on the LSI whose operation is to be analyzed under the same conditions as for a good LSI, for example, with the same full chamber pressure applied, and this is then recorded by photography. The two photographic images thus obtained are compared visually and the occurrence of a defect and the location of the defect are detected by finding areas with different contrasts at corresponding positions.

However, the above-mentioned method of comparing photographic images requires an extremely large amount of time and effort since the comparison is performed visually. For this reason, ζ et al. have proposed a technique in which this comparison operation is automatically performed by an image processing device using an electronic computer. The method using this technology is 2
Of the two image memories, 10,000 are stored with the potential contrast image of the good LSI, and the other is stored with the potential contrast 1&l of the LSI for which operation analysis is to be performed, and the volumes of both memories are sequentially compared using a computer. It is something. The simplest comparison method using an electronic counter/J4-machine is to subtract all the memory contents, and by extracting all the parts where the result of this subtraction is not 0, it is possible to find 1 defective part. Note that the bright and dark states of the potential contrast image correspond to the voltage levels, but are they normal logical operations? In the LSI to be implemented, this 1"1. is logic level II I It
Alternatively, it corresponds to It □ If. Therefore, the most simplified method is 1. As a method of failure analysis, it is effective to binarize the potential contrast image according to the total brightness state VC and judge it as a logic level, and this method has been adopted in the past.

However, when using such a method, the problem with the secondary Hiroko image is that, in addition to the potential contrast, the contrast caused by the convex image state on the LSI surface and the emission efficiency of secondary electrons due to the material components are included in the secondary Hiroko image. This is what the difference-based contrast is all about. In particular, contrast caused by surface irregularities is called an edge effect and becomes a noise component that is difficult to remove from the n1 potential contrast image.

There are many irregularities on the surface of an LSI in addition to the wiring made of aluminum, and it is difficult to simply remove all the edge effect components by binarization. It is not possible to accurately detect the occurrence of a defect and the location of the defect.

Moreover, in the conventional method, contrast images are compared over all areas of the LSI, which has the disadvantage of lengthening the detection time.

[Purpose of the invention]

Is this invention due to the above circumstances? The purpose of this is to accurately detect the occurrence of defects and the location of defects when using an EB tester to analyze defects in semiconductor integrated circuits, and to reduce the time required for analysis compared to conventional methods. The purpose of this invention is to provide a complete failure analysis method for semi-four-cup integrated circuits that can be shortened.

[Invention? : Essential]

This invention focuses on the fact that in a semi-bound integrated circuit that performs logic operations, it is possible to perform failure analysis using only a potential contrast image in the wiring area. The size of the layout a in the semiconductor integrated circuit is a! Two image memos IJ' (i=prepared) set to match the width of the area, one of which contains a binarized contrast image by secondary electrons obtained from a good integrated circuit. The other memory stores image information that has been converted into a full contrast image obtained from a centralized circuit that performs failure analysis, and the By comparing only all the information in the memory block at the position corresponding to the wiring area2, it is possible to detect the occurrence of defects and the location of defects with complete accuracy ((2). A large number of integrated circuit failure analysis methods are available.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an apparatus used to implement the method of the present invention. In the figure, 11 is L
This is an EB tester that scans and irradiates the SI with an electron beam to obtain a contrast image using secondary electrons. The contrast image produced by this EB tester 11"'C is converted into II I II or I
f □ Converted to II's dQ/reason level, it is reported as an anti-image mystery news. Then, due to the lack of a good LSI, the above 2
The image information obtained by the value conversion circuit 12 is stored in the first image memory 1.
2 above for LSIs stored in 3 and performing n1 failure analysis
The image information obtained by the value conversion circuit 12 is stored in the second image memo 1,
114.

Above 1. As shown in FIG. 2, the second image memo') 13.
” In the 12 areas of X 12, in the vertical direction, for example, Y1 ~
It is configured to have 144 memory blocks 21f divided into 12 areas of Y12. Furthermore, the valley memory block 21 has a total of 3600 memory cells 22 of f160x60 and is made of paulownia W. And notes on each image! 713, the size of one memory block 21 in 14 is observed by EB tester 1;
b LSI (7) The expansion magnification equal valley line conditions in the EB tester 11 are set so as to match the width of the self-line area.

tEB tester 11'T: Suppose that when all non-defective LSIs are observed, a contrast image as shown in FIG. 3 appears. In the figure, the diagonal metal group part 9 in the lower left is in a dark state in the N1 region where it is at a high potential, and it is in a dark state in the diagonal i! #The gold-colored part is bright in the arm side region where the potential is maintained at a low potential. Sara←゛koslant 1:
The remaining portion that is not exposed deep is a region other than wiring, and this region is in a bright state. Note that this contrast image is shown to be overlapping with each memory block 21 of the first image memory 13. From such a contrast image, the 21-direction conversion circuit 12 converts the dark portions to Il I If logic level and the bright portions to l!
□ Obtain image information converted to I+ logic level, and this image information is then stored in the first image memory 13.

Next, when observing an LSI that performs 4-band analysis using the EB tester 11, a contrast 1 image as shown in Figure 4 is obtained.
That's it. In Figure 4, the 1ζ area with diagonal lines in the lower left and the lower right, and the shaded area with no sails are the same as in Figure 3, where the wiring is kept at a high potential. The bright part is the wiring area where the potential is maintained, the bright part is the area other than the wiring, and the part where all the sputum lines in the lower left 9 and lower right 9 are applied is the dark part of the noise component due to the edge effect. ``There is C. From the contrast image containing such noise components, the binarization circuit 12 converts the dark parts into the If I If logic level and the bright partials II □ II logic level, respectively, as described above, and converts the entire image information. After this, this colossus information is stored in the second picture 1 family memory 1.
4 is stored.

1st, m 2 + i]
4vtc-ttz so that the image information is stored in both memories 1.3'.

Image information is read out from the corresponding valley memory blocks 21 of 14 and supplied in parallel to the comparison circuit 15 shown in FIG. 41A. Here, since the potential contrast related to the operation of the LSI is only in the wiring area, both the image memories 13',
The information to be read from the memory block 74 is only the wiring area indicated by diagonal lines in FIG. Only the information in one memory cell 22 may be viewed. Comparison circuit 15 has both notes! 713,
The matching comparison of the information from 14 is performed sequentially, for example, by subtracting the information. If a match is detected (1nn-), it can be determined that the operation at that position is normal; on the other hand, if they do not match, it can be determined that the operation at that position is defective. The above comparison results are recorded in the comparison result memory 16 as the logic levels of Il I II and II oI+. Art 4ru. FIG. 5 shows the storage pattern of the comparison result memory 16 obtained by comparing only the information corresponding to the plated area among the image information based on the contrast image of FIG. 3) and the contrast image of FIG. 4. FIG. In Figure 5, the shaded area at the bottom left 9 is the non-matching area l) 11
It is set to 111 logic level. The 1"L displayed on the display 17 in accordance with the contrast of the entire brightness and darkness of the contents of the comparison result memory 16 can be used to detect defective areas ygT in the wiring area with the minus eye. Note that both image memos I ) To read out all the information corresponding to the wiring area from 13 and 14, display this information on the display 17 when obtaining a contrast image with the EB tester 11, and display the wiring area at this time in the first and second areas. This 1''L is converted into an address in the image memory 13, 14 and stored, and when reading information, the first . It is possible to address the second image memory 3.14.

In this way, in the method of the above embodiment, all failure analysis is performed by comparing only the image information corresponding to the wiring area of the LSI, so the contrast components associated with the unevenness of the frowning surface outside the wiring area are removed first. A comparison meeting can be held. Therefore, it is possible to accurately detect the occurrence of defects and all defective locations. And number one. Second image memo IJ
Since it is only necessary to compare the information of the memory block 21 that corresponds to the wiring area among i 3 and 14, the time required for comparison can be made shorter than before. l
It is possible to reduce the total amount of time required for analysis.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made. For example, in the method of the above embodiment, a case has been described in which a curved image information based on a contrast image obtained by actual observation with a good LSI kEB tester is stored in the first image memo IJ13. Recently, LSI patterns have been designed using all electronic meters, and the wiring pattern at this time is F7R.
lI of a good LSI in advance using c! The second image information may be stored in the first image memory 13. In cases like Manotako, force 1. 2nd Be 1ITi4 image memo +)
Address designation for reading information from 13714 may be performed based on the wiring pattern information.

Further, in the above embodiment, the ratio v h in the comparator circuit 15
Although a case has been described in which the comparison results are stored in the comparison result memo IJ 16, the comparison results may also be stored in the second image memory 4.

〔Effect of the invention〕

As explained above, according to the present invention, the memory block is composed of a plurality of memory blocks, and the size of each memory block is set to match the width of the wiring area in the semiconductor integrated circuit.
, and two image memories were prepared to store all the image information corresponding to contrast 1 and 2, and of these, only the friend information corresponding to the wiring area was read out and compared. Furthermore, it is possible to provide a failure analysis method for an integrated circuit that is capable of accurately detecting a defective part and reducing the amount of time spent on analysis.

[Brief explanation of the drawing]

FIG.
2 is a block diagram showing the configuration of the image memory shown in FIG. 1, and FIGS.
Fig. 1 shows the contrast image obtained with the EB tester, and Fig. 5 is a comparison of Fig. 1.Memory pattern of memory? FIG. 11... EB tester, 12... Binarization circuit, 13...
...first image memory, 14...second image memory,
15... Comparison circuit, 16... Comparison result memory, 17.
-Display device, 21...memory block, 22...memory cell. Client's agent Patent attorney Suzue Takeshi Buta-゛“′”S
I11---Ge>> )-)-Me

Claims (1)

[Claims] The contrast image based on the secondary electrons generated by irradiating the semiconductor integrated circuit with an electron beam while scanning the entire semiconductor integrated circuit is binarized to protect the image information, and the size of the valley memory block is determined by The above image information is stored in a first image memory which is configured of n1 memory blocks set to match the width of the wiring area.
Among the image information stored in the image memory of 7, the information in each memory block corresponding to the wiring chain acid is stored in a second memory block that stores the image information obtained from the performance circuit of the non-defective product & the corresponding information. The information in the corresponding memory block of the image memory is compared to
A method for analyzing defects in semiconductor integrated circuits, which is characterized by detecting w.