JPS59122128A - Cmos counter circuit - Google Patents

Abstract

PURPOSE:To output a non-inverting signal and an inverting signal in the same phase by a clock signal of single phase by constituting a dynamic counter circuit of a CMOS to quicken the speed and make the power consumption low. CONSTITUTION:When the level of an input is an L, then an MOS transistor(TR) T1 is turned off and a TRT2 is turned on. As a result, a point C goes to an H level and a T5 is turned off. Further, since the level of the input to a T3 is L, a voltage at a point (d) remains at the preceding level. When the voltage stored at the point (d) is in the L level, then a T8 is turned off and a T7 is turned off. Since a T9 is turned on, a point (e) reaches the H level and a non-inverting output Qn goes to the H level. Then, an output point (f) of inverters T10, T11 goes to the L level. Suppose that the input is changed to the H level, the point (d) goes to the H level and the output level at the points (e) and (f) is unchanged. When the input goes to the L level again, the point (e) goes to the L level and the point (f) is inverted into the H level.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a MOS transistor circuit, and particularly to a CMO transistor circuit.
The present invention relates to a CMOS counter circuit composed of three circuits.

(2) Technical Background Counter circuits using bipolar transistors consume a large amount of power. Therefore, in recent years, counter circuits using CMO3 circuits with low power consumption have been used. As is well known, CMO3 is a combination of an N-channel MO3I-transistor and a P-channel MO3I-transistor, which avoids the formation of a current path from the power supply to the ground for one clock input signal. , which enables operation with low power consumption.

Incidentally, counter circuits include static counters in which a counter value is held, and dynamic counters in which the counter value is lost unless a clock signal is input within a specific time.

The dynamic counter circuit operates faster than the static/7-power counter circuit, so if the dynamic counter circuit is constructed from CMO3, a high speed counter circuit with low power consumption can be obtained.

(3) Prior Art and Problems As shown in FIG. 1, the conventional Guinamisoku CMOS counter is similar to the first transfer gate 3 consisting of N-channel and P-channel MOS transistors 1.2 connected in parallel. P channel MOS
) A first inverter circuit 6 consisting of transistors 4 and 5 connected in series, a second transfer gate 7 having the same configuration as the first transfer gate and inverter circuit, and second and third inverter circuits 8 and 9. are connected in series in a closed loop. N of first transfer gate 3
Channel MO3) Langisk l and P channel MOS
A clock signal T and an inverted clock signal T are applied to the gate of transistor 2. Conversely, an inverted clock signal T and a clock signal T are applied to the gates of the N-channel MOS transistor and the P-channel MO3I-RANDIS of the second transfer gate 7, respectively. The output of the inverter circuit 8 becomes the positive phase output Q, and the output of the inverter circuit 9 becomes the inverted output Q.

1- Transfer gate 3 and transfer gate 7 are ON
, OFF operate in reverse. That is, when transfer gate 3 is ON, transfer gate 7 is OFF.
When the transfer gate 1-3 is OFF, the transfer gate 7 is turned ON. For example, when the inverter circuit 9 is at a low level (hereinafter referred to as L level), the clock signal 1' is at a high level (hereinafter referred to as H level) and the MOS transistor 1 is turned on, and when it is at H level, the inverted clock signal T is at L level. MO3I-Ranjisk 2 is turned OFF. That is, the clock signal T
When is at H level, transfer gate 3 is turned on.

Since the clock signal T which is inverted with respect to the gate input of the first transfer gate 3 is input to the gate input 12 of the second transfer gate 7, the clock signal T is low.
It turns ON when the level is reached.

FIG. 2 is a timing clock chart showing the operation of the conventional CMOS count circuit.

The transfer gate 3 is turned OFF by the BLACK and TUCK signals T1.
N, the output of the inverter circuit 9, that is, the H level is added to the input of the inverter circuit 5, and the point a becomes L level. The 1-transfer gate 3 is turned off by the next clock signal T+', and the above-mentioned I] level remains applied to the inverter circuit 5. This is MO3I
- The impedance of the input of the transistor is almost infinite, and it is kept constant by stray capacitance such as wiring. The transfer gate 7 is turned on by the clock signal T+', and the output of the inverter circuit 5, that is, the signal at point a is applied to the inverter circuit 8. As a result, the output of the inverter circuit 8 becomes H level, and the H level is output as the positive phase output Q. Further, the output is inputted to an inverter circuit 9, and 15 levels are output from the output as an inverted output stone. Next, the transfer gate 3 is turned ON by the clock signal T2, and the output of the inverter circuit 9, that is, the L level, is transferred to the inverter circuit 5 via the transfer gate 3.
join. At this time, since the transfer gate 7 is OFF, the positive phase output Q and the inverted output Q do not change. The next clock signal T2' turns on the transfer gate 17 and turns off transfer gates 1-3, and as mentioned above, the level at point a is input to the impark circuit 8, and further inverted and sent to the inverter circuit 9. Mouth. This results in positive phase output Q.

The inverted output Q changes to I7 level and H level, respectively. The following steps are repeated sequentially. In other words, output Q.

Q is a signal obtained by dividing the clock signal T by two.

The operation of the circuit shown in FIG. 1 is the same as that of a 1-bit counter, and by adding the output of this circuit to the clock signal input of the next stage, multi-stage counting becomes possible.

The conventional CMOS counter circuit requires a positive phase signal and an inverted signal as clock signals. However, as is clear from the above-mentioned circuit, since the normal phase signal is converted into an inverted signal via an inverter, the normal phase signal and the inverted signal have a drawback that their phases do not completely match. This has the problem that when a multi-bit counter is configured, for example, the second stage transfer gates are turned on at the same time, making it impossible to divide the frequency. Additionally, since a negative phase signal is generally created by inverting a positive phase signal, their phases may not match perfectly, and similar problems may occur if such a signal is input as a clock signal. It had Furthermore, since a circuit that outputs two phases, that is, a positive phase and a negative phase, has an impark, the speed is slow and the above-mentioned counter etc. cannot perform high-speed counting.

(4) Purpose of the Invention The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a CMOS counter circuit that counts at extremely high speed using a single-phase clock signal.

(5) Structure of the Invention The present invention is characterized by a first one-conductivity type Mos+ transistor to which an input is applied to the gate, and a second transistor to which an input is applied to the gate and whose electrode is connected to a power source. an opposite conductivity type MO3) transistor, a second one conductivity type MOS transistor whose input is applied to gate 1~, one electrode of the first one conductivity type MOS transistor, and the other side of the first opposite conductivity type MO3I transistor; A third one conductivity type MO3I- whose gate is connected to the first connection point with the electrode.
a second opposite conductivity type MO3 having a first series connection body made of a randisk and whose other electrode is grounded; a gate coupled to the first connection point; and one electrode connected to a power source;
an I-transistor, a fourth one conductivity type MO3I-transistor having a gate connected to the first connection point, one terminal of the first series connection body, and the other electrode of the second opposite conductivity type transistor. a second series connection body consisting of a fifth one-conductivity type MO3I-Randisk having a gate connected to said second series connection body, the other terminal of which is grounded; and a third opposite connection body having a gate connected to said second connection point. a conductivity type MOS transistor and a fourth opposite conductivity type MO3 whose input is connected to the gate;
) a third series connection body consisting of a transistor, one terminal of which is connected to a power source, and a third connection point between one terminal of the second series connection body and the other terminal of the third series connection body; and an inverting circuit whose inverting output is connected to the other electrode of the first one-conductivity type MOS transistor.
It's in the counter circuit.

(6) Examples of the invention Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 3 shows a circuit diagram of a first embodiment of the invention.

The embodiment shown in FIG. 3 is a P-channel MOS transistor T2.
．． T5. Ta, T9. Tl + and N channel MO3)
Transistor T1. T3. Ta,,'Tr+.

Consists of TV and TIO. Input IN is Mo3I
- transistor T2. T9 gate and N channel MOS
Input to the gates of transistors TI and T3. Mo3)
The drain of the transistor T2 is connected to the power supply Vcc. Mo3) The source of transistor T2 is connected to the drain of T1, and its connection point C is Mo3) transistor Ta.
, T5. connected to the respective gates of T6. The source of Mo3I-transistor T1 is connected to the inverting output Q.

Mo3) The transistors T3 to T5 are connected in series between the power supply and the ground, with the drain of the MOS transistor T5 being connected to the power supply Vcc, and the source of the MOS transistor T3 being connected to the ground. MOS transistor T! The connection point d between the source of Mo3) and the train of transistor Ta is Mo3) transistor T7. Joins the gate of T11. Furthermore, MOS transistors 'F5 to T9 are also connected in series between the power supply and ground, and the drains of MOS transistors 1 and 9 are connected to the power supply Vcc, and transistors T6
The sources of each are connected to ground. A connection point e between the source of the MOS transistor T8 and the drain of the transistor T7 is output as a positive phase output Q, and is also connected to the MOS transistor T++.

Input to the gate of T+o. Mo3I-ransistor T+
+, T''+o are also connected in series between the power supply Vcc and the ground, the drain of T++ is connected to the power supply Vcc, the source of T++ is connected to the ground, and the connection point f is outputted as an inverted output Q.

The table (see next page) shows the ON and OFF states of Mo3) transistors TI to T++ and the logic level at points c-f with respect to the input signal of the first embodiment of the present invention. below,
The operation of the first embodiment of the present invention will be explained using a table. It is assumed that the inputs in the table change from the left to the right of the table.

First, assume that the input is at L level. At this time, Mo3I
- The transistor T1 is OFF, Mo3) The transistor T2 is turned ON. As a result, point C becomes H level and Mo3I-
The transistors 1 and 5 are turned off.

Also, since the input of Mo3I-ranjisk T3 is at L level, Mo3) ranjisk T3 is shown as OFF, and furthermore, what is connected to that point, that is, point d, is Mo3I-ranjisk T3.
3) Ranjisk T? , T8, the voltage at point d is held at the previous level.

At this time, the Mo3I resistor T4 is ON, but since it is connected in series with the Mo3I resistor T3, the level does not affect the point d. This holding time is Mo
3I - Drain electrode of transistor T3, Mo3) Source and drain electrode of transistor T4, Mo3) Source electrode and wiring capacitance of transistor T5, determined by capacitance such as wiring capacitance and leakage current flowing to the gate of each MOS transistor connected to point d . The present invention relates to a counter, etc., and the repeated changes in the H3L level of the input signal are much faster than the above-mentioned holding time.

If the voltage held at point d is at L level, Mo3I
- The transistor T8 is turned on, and the Mo3'h transistor T7 is turned off. That is, by inputting L level, Mo
Since the S transistor T9 is ON, the point e becomes H level by turning on the Mo3) transistors TB and T9. At this time, MOS transistor T6 is ON, but MOS transistor T7 is OFF, so MOS transistor T? , T6, no current flows through them. Point e is output as a positive phase output Qn. That is, the positive phase output Qn
is I (level).

Furthermore, the MO3I-transistors T+o and T++ constitute an inverter circuit, and the output point f thereof becomes an L level. Next, assume that the input signal changes from L level to H level. Due to the change in this signal, the MOS transistor T1 is turned on, and the MO3 transistor T1 is turned off.

Since the source of MO3I-transistor T1 is at L level at this time, point C is at I7 level. As a result, M.O.
S transistor T5 is turned on. On the other hand, since the input level, that is, I (level) is input to the MOS transistor T3, the level at point C is input to the MO3 transistor T4, so T4 is turned off. That is, the point d becomes the voltage level of the power supply Vcc, that is, the I] level via the MOS transistor T5. At this time MO3
Although the I-transistor T3 is ON, it has no effect on the level because it is connected in series with the MOS transistor T4.

This H level is input to the MOS transistors Tt and Te, and the MOS transistor T7 is turned on and the MOS transistor T8 is turned off. On the other hand, the H level is input to the MOS transistor T9, the L level is input to the MOS transistor T6, and the MO3I-transistor T6.

I9 is turned OFF. Since the MOS transistors Ts to T9 are connected in series, the previous level, ie, H level, is maintained at point e. That is, the positive phase output Qn remains at the l-I level, and the inverted output 0n remains at the L level.

Next, when the input becomes L level again, MOS transistor T1 turns OFF, MOS transistor T2 turns ON,
Point C becomes H level. As a result, MO3I-transistor T5 is turned off. Since the input of MOS transistor T4 is at the level of point C, that is, 1 level, MOS)
Transistor T4 is turned on. On the other hand, since the L level is manually applied to MO3I-transistor T3, MOS transistor T3 becomes OFF, and MO3I-transistor T3
.

] 5 is OFF, the current I4 level is maintained at point d. If point d is )I level, then MOS)
Transistor Tθ is OFF, MOS) transistor T7 is OFF
It becomes N. Also, since the I4 level is added to the gate of MO3I-Landisk T6 as well as the level of C point, M
The O3+- transistor T6 is also turned on. That is, MOS
) Lanjisku 'l' 6.

T7 is turned on, and the MOS transistor T9 is turned on, but since the MOS transistor T8 is turned off, the point e becomes L level. Similarly to the above, the inverting output Q at point f becomes the I level by the in-hark circuit constituted by the MOS transistors T1o and T1+.

Further, when the input signal reaches the II level, the MOS transistor [2] is turned off. MOS1 ~ Ranjisk T1
An input signal is applied to the gate of MO3I-transistor T1, but its source is at the same level as the inverted output Q.
is OFF. As a result, the previous H level is maintained at point C.

If point C is at H level, MO3I-transistor T
5 is OFF, and the input level, that is, the H level, is input to the MOS) transistor T3, and the 0 point level, that is, the H level is input to the MOS) transistor T4. O
N, and point d becomes level 17. This allows M.O.
The S transistor T8 is turned on, and the MOS transistor T7 is turned off.

Furthermore, the gate of the MOS transistor T9 is connected to the input signal H.
Since the level is added and the MO3+- transistor T9 is turned off, the point e, that is, the output Qn, is maintained at the previous L level. Note that although the MOS transistor T6 is ON at this time, it does not affect the operation because the MOS transistor T7 is OFF. Since point e is at L level, point f, that is, the inverted output Qn, is at H level. Further, when the input signal goes to L level, the MOS transistors TI, T3 . T5. T? , Tl + is OFF,
, MOS I-transistor T2. T4. T
6°Ta, T9. Tlo is turned ON, and points C to e become H, L, H, and L levels, respectively. The above-described level changes are sequentially repeated as the input signal changes.

FIG. 4 shows the level relationship between the input signal and points C to F. The zero point, that is, the positive phase output Qn, is a frequency-divided signal with respect to the input signal. Further, the point f, that is, the inverted output Qn, is a signal inverted from the signal at the 0 point.

This operation, that is, the 2 operation, is the same operation as a 1-bit counter, and can also be operated as a ■-bit counter.

FIG. 5 shows a circuit diagram of a second embodiment of the invention.

The first embodiment is a MOS) transistor T1o.

The inverter circuit composed of T11 is different. That is, in the second embodiment, the output at point 0 is output as the positive phase output Qn, and the MOS transistor T12
input into the gate. The source of MOS1 transistor T12 is grounded, and its drain is connected to the source of MOS transistor ', and the gate of MOS transistor T3.In the first embodiment, the output of Inhark is at H level and L level. However, in the second embodiment, there is an L level and an open state, that is, a high impedance state.In the explanation of the first embodiment, the MO
There existed a state in which an H level was applied to the gate of the S transistor T1. At this time, MOS transistor T1 is OF
It was F.

In the second embodiment, the MOS transistor T12 is turned off, so the same operation occurs.

Third. The first aspect of the present invention shown in FIG. In the second embodiment, MO3I-transistors T3 and T4.

T6 and T7. Even if the signals input to the respective gates of the series connection of Te and T9 are switched, the same operation will occur. For example, in MOS transistors T3 and T4, the 0 point is connected to the gate of MO3') transistor 13, and an input signal is input to the gate of MOS transistor Ta. Furthermore, in MO3I-ranjisku T6 and T7, point d is connected to the gate of MOS transistor T6, and 0
points are connected to the gates of MO3I transistors T7, and in MO3I transistors T8 and T9, points d are connected to the gates of MOS transistors T9, and M
It is also possible to input an input signal to the gate of O3+- transistor T8.

(7) Effects of the Invention As described above, the present invention relates to a CMO3 circuit, and the present invention not only enables a counter that does not require two-person labor or a two-phase clock, but also enables high-speed operation. It is possible to obtain a CMOS counter operating in one cycle.

[Brief explanation of drawings]

Figure 1 is a conventional CMOS counter circuit diagram, Figure 2 is a timing chart diagram of a conventional CMOS counter circuit, and Figure 3 is a diagram of a conventional CMOS counter circuit.
Figure 5 shows the first embodiment of the present invention. CMOS counter circuit according to the second embodiment. FIG. 4 is a timing chart diagram of the counter circuit according to the first embodiment of the present invention. T+, T3. Ta, T6. T7. Tlo. Tl2...N channel CMOS) transistor, T
2. T5. Ta, T9. T11...P channel C
MO3I-Randysk. O 3 Fig. O 4 Fig.

Claims (3)

[Claims] (1) The first conductivity type M to which input is to be applied to the gate
an OS transistor, a first opposite conductivity type MOS transistor with an input applied to its gate and one electrode connected to a power supply, and a second monoconductivity type MO3I having an input applied to its gate.
- a third one-conductivity type transistor whose gate is connected to a first connection point between one electrode of the transistor and the first one-conductivity type MO3+ transistor and the other electrode of the first opposite-conductivity type MO3I- transistor; MO3) A second opposite conductivity type MO3) transistor having a first series connection body in which the transistor is connected and the other electrode is grounded, and a gate coupled to the first connection point and one electrode connected to a power supply. and the first
a fourth conductivity type M having a gate connected to a connection point of
a fifth one conductivity type MO3 having a gate connected to an O3I transistor, one terminal of the first series connection body, and the other electrode of the second opposite conductivity type MO3I transistor;
a second series-connected body consisting of an I- transistor whose other terminal is grounded; a third MO3) transistor of the opposite conductivity type whose gate is connected to the second connection point; and a third series-connected body whose input is connected to the gate. a third series connection body consisting of four opposite conductivity type MOS transistors, one terminal of which is connected to a power supply;
The inverting output is coupled to a third connection point between one terminal of the second series connection body and the other terminal of the third series connection body and is connected to the other electrode of the first monoconductivity type MO3) transistor. A CMOS counting circuit consisting of an inverting circuit and an inverting circuit. (2) The inverting circuit has a sixth MO3) transistor of one conductivity type, each having a gate connected to the third connection point, the other electrode of which is grounded, and a fifth opposite transistor, one electrode of which is connected to the power supply. The inverted output is a connection point between one electrode of the sixth one conductivity type MOS transistor and the other electrode of the fifth opposite conductivity type transistor. The CMOS count circuit described in item 1. (3) The inversion circuit has a gate connected to the third connection point, and the other electrode is grounded.
3. The CMOS counter circuit according to claim 1, wherein the CMOS counter circuit comprises a 3L transistor, and one electrode of the seventh one-conductivity type MOS transistor is connected to the other electrode of the first one-conductivity type MO3L transistor. .