JPS59122005A - Pulse-width modulating power amplifier - Google Patents

Abstract

PURPOSE:To obtain an efficient pulse-width modulating power amplifier by utilizing the charge storage time of transistors (TR) in a driving cirlcuit to prevent the driving voltage of an output stage from being biased forwardly at the same time. CONSTITUTION:When a positive signal is impressed to an input and TRs Q1 and Q2 are OFF and ON respectively, TRs Q9, Q3 and Q6 are OFF and TRs Q10, Q4, and Q5 are ON, so charges are accumulated in respective base areas of the TRs Q10, Q4, and Q5. In this case, the gate of a FETQ8 is biased forwardly in the middle of the switching operation of the output stage, but the gate of an FETQ7 is biased reversely and no current flows through the FETQ7, so that no cross current is generated. Thus, both FETs Q7 and Q8 are prevented from being biased reversely at the same time. Consequently, the power loss of each FET is reduced greatly to improve the efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation (PWM) power amplifier, and more particularly to a PWM power amplifier that minimizes power loss occurring during output stage switching.

Conventionally, a configuration as shown in FIG. 1 has been used near the output stage of a PWM power amplifier. The figure shows an example in which a MOSFET is used as a switching element in the output stage.

In the figure, 1 indicates the S pulse width modulation signal 75 (the input terminal to which the input is applied, NPN), runci y, pQ, o, and P
NP) is connected to each base of transistor Q.

The emitters of Ql and Q2 are connected, and resistors R,,R
, is grounded through. A capacitor C1 is connected in parallel to the resistor R7.

On the other hand, as a power supply, the power supply for the output stage is made based on B+, +B+, and 9Bz (=+B+ + V'+) and B
, (=+B+-Vt), and B+ (two BIVI) and B, (=-B, +V, ) made based on -B1
is available.

The collector of transistor Q1 is connected to one end of resistor R3, NP
N) transistor Q, and PNP) connected to each base of transistor q. Q3 and Ql are connected at their emitters and are led to the gate of P-channel MO8FET Q7.

Also, the collectors of Q= and Ql are connected to Bt and B, respectively, and the source of FBTQ is connected to B.

Sara K, above Rs, Ql, Ql, Q? With a completely symmetrical configuration, R4, Qs, Q, a, and Qa are connected,
The drains of FETs Q7 and Q8 are connected to each other, and are led to output terminal 2 through a low-pass filter consisting of inductor L1 and capacitor C2. Output terminal 2
A load 3 is connected to the . Note that a bias resistor R1+ is connected between the input terminal 1 and the ground.

In this configuration, the operation will be explained next. 2--@ in FIG. 2 are voltage waveforms at each point 2--@ in FIG.

When a PWM signal is applied to input terminal 1, FETQ'7
．． Each gate voltage of Q8 has a waveform as shown in FIG. 2 @, 2, and a forward bias is alternately applied to each gate.

Then, at the drain of Q,, Q, a waveform as shown in Fig. 2 is obtained.

A positive signal is input to the input, transistor Q1 is turned off,
) When transistor Q2 is ON, transistor Q3. Q,
is ON, and transistors Q, ,Q, are OFF, so the base regions of transistors Q, ,Q, ,
Charge is accumulated.

When the input is inverted and transistor Q1 is turned on and transistor Q2 is turned off, the accumulated charge in transistor Q3 is strongly extracted through transistor Q, but the accumulated charge in transistor Q6 only flows out through resistor R4. As in td in Figure 2 O, F
It takes some time until the gate voltage of ETQ8 starts to reverse.

Similarly, at the moment when the input becomes negative, it takes some time for the accumulated charge in transistor Q to disappear, and the gate voltage of FET Q causes a slight delay as shown in td2 in Figure 2 @. . Therefore, there is a time when both FETs are forward biased.

In Figure 2, during the switch operation of the output stage (tl)
Looking at FB TQ7. Since forward bias is applied to the gates of both Qa and the drain-source voltage VD is also in the forward direction, a forward current tends to flow in both Qa.

Therefore, at this point, power supply ('-1-Bl)→
A large current flows through the path of FETQ7 → FETQs → power supply (-Bl), causing a large power loss in each FET, and the load line of the element may exceed its safe operating area, leading to destruction of the element. .

This current is called a cross current, and its presence significantly deteriorates the efficiency of the output stage and requires a wide safe operating area for the elements used. Therefore, when configuring a pulse width modulation power amplifier, This was a major obstacle.

Furthermore, since the collector-pace capacitance of the next stage transistor exists in parallel with the resistors R3 and R in the drive circuit, if the resistance value is large, the switching speed will be slow.

Furthermore, as mentioned above, the transistors Q,,Q,.

It is also a path for removing the accumulated charge, and it is desirable that the resistance value be within several hundred ohms.

On the other hand, the transfer conductance Gm of MOSFET is 1 to
Most of them are 2 Siemens, and when a large drain current is required, such as in a high power amplifier, it is necessary to have a gate voltage amplitude of 10 volts or more.

Therefore, the voltage across each of the resistors R3, R, must also be varied by 10 volts or more.

For example, if the resistors R8 and R4 are each 330Ω, when the transistor Q1 or Q2 is conductive, the collector current of each transistor is required to be more than 30 mA, even assuming that hfe of the next stage transistor is infinite.

At this time, if the voltage of power supply B, B is ±60V,
When transistors Q, Q2 are conductive, ■a z = 5
．． QV.

■ Operates at a==3QmA, collector loss Pa at this time
=1.5W.

Actually, in order to drive the interelectrode capacitance of the output stage at high speed, it is necessary to supply a relatively large current to the gate during switching, so the transistors Q, Q2 have
A large current is required instantaneously.

As described above, the transistors Q, Q2 require elements with a wide safe operation area and large collector loss.

This invention was made to eliminate the drawbacks of the conventional devices as described above, and utilizes the charge accumulation time of the transistor in the drive circuit to ensure that the drive voltage of the output stage elements becomes forward biased at the same time. It is an object of the present invention to provide an efficient pulse width modulation power amplifier by preventing this.

An embodiment of the present invention will be described below with reference to the drawings. Third
In the figure, the same parts as in FIG. 1 are represented by the same symbols.

Regarding the positive side, disconnect the connection HA between the base of transistors Q, ,Q, and the collector of transistor Q,
A PNP transistor Q is connected to the collector of transistor Q1.
, connect the base of. The emitter of transistor Q9 is connected to power supply B, and the collector is connected to transistor Qλ.
, Q4 and one end of resistor R6. The other end of resistor R8 is connected to power supply B3.

On the negative side, the configuration is symmetrical to that of the transistor Q. ,
A resistor R6 is used.

Next, the operation of this invention will be explained. In this case, a signal having the opposite phase to the signal applied to the input terminal 1 is obtained at the 0 point, which is different from that in FIG.

FIG. 4 shows examples of waveforms at various parts.

A positive signal is applied to the input, transistor Q1 is turned off,
) When transistor Q, is ON, transistor Q,, Q
,, Q6 is OFF, ) transistor QIOII Q4q
Q4. Charge is accumulated in each base region of Q.

Input is inverted, transistor Q1 is ON, Q2 is OFF
When this happens, transistor Q9 turns on, removes the accumulation of q, and turns on Q. Therefore, the gate voltage @ of FETQ quickly rises.

However, on the negative side, even if transistor Q2 is turned off,
QIo and Q2. Since it takes time to open until the accumulation of FET Q is eliminated, the gate of FETQ is inverted after a time delay as indicated by td in Figure 4. Similarly, at the moment when the input becomes negative, a delay as shown in td4 in Figure 3 occurs.

In this case, looking at the middle of the switch operation (t2) in the output stage, the gate of FETQ8 is forward biased, but the gate of FETQ is reverse biased, and FET
Since no current flows through Q7, no cross current occurs.

In this way, FETQ7. A situation in which both Qa are forward biased simultaneously can be avoided.

This allows the power loss of each FET to be significantly reduced, improving efficiency.

Furthermore, since the change in voltage across the resistors R3, R, does not reach even 1 volt, it is possible to suppress the current value flowing through the transistors Q, Q2 to a small value.

For example, if a resistor Rs, R<K 220Ω is used, the collector current of the transistors Q, , Q, is approximately 3 m
The value is A plus the base current of the next stage.

Compared to conventional circuits, the power loss of transistors Q, , Q2 is significantly smaller, and the selection of elements is easier and cheaper elements can be used, so the cost can be reduced by reducing the cost of transistors Q, , Q, , you can turn it around.

Note that when transistors Qo and QIo turn from ON to OFF, it takes longer than expected, and on the positive side, transistor Q8. On the negative side, if the storage time of the transistor Q is sufficient and the above effect can be obtained, it is effective to use the method shown in FIG.

That is, the signal applied to input terminal 1 is connected to the capacitor C on the positive side.
8 and resistor R7, and differentiated by capacitor C4 and resistor R8 on the negative side, and transistor Q through resistors R9 and Rlo, respectively.
1□, drives Q12.

Therefore, for example, when the input is reversed from negative to positive, transistor Q+t is momentarily turned on and drains the accumulation in transistor QIO, and when the input is reversed from positive to negative, transistor Q9 is similarly activated by transistor Qo. When you pull out the accumulation of

In this example, capacitors C, ,C, are connected to input terminal 1, but they may also be connected to the emitters of transistors Q, ,Q2.

As described above, the present invention is configured such that the drive voltages of the output stage are not simultaneously biased in the forward direction, so that cross current does not occur and it is possible to provide an efficient pulse width modulation power amplifier. can.

In addition, the safe operating area of the elements used in the output stage can be narrower than in the past, making it easier to select the elements.
An inexpensive one can be used.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration from the excitation stage to the vicinity of the output stage of a conventional pulse width modulation power amplifier, FIG. 2 is a diagram showing an example of voltage waveforms at each part of FIG. 1, and FIG. FIG. 4 is a diagram showing an example of voltage waveforms at each part of FIG. 3, and FIG. 5 is a diagram showing another embodiment of the invention. R,, R,, R7, R8... Resistance Q,, Q,. r QII+ Q10... Transistor patent applicant Pioneer Corporation Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] a resistor through which a current according to a pulse width modulation signal is transmitted, one end of which is connected to a power supply; a transistor whose emitter is connected to the power supply line and whose base is connected to the other end of the resistor;
A pulse width modulation power amplifier circuit, characterized in that a signal for driving an output stage is obtained from the collector of the transistor.