JPH04128435U - Isolated drive circuit for power MOS FET - Google Patents

Abstract

(57) [Summary] [Purpose] To reverse bias the gate and shorten the turn-off time of a power MOS FET even when the ON pulse width t ₁ is narrow. [Configuration] A capacitor 1 is connected between the source S ₁ of the power MOS FET 10 and the terminal S-2 of the pulse transformer 6.
3 and a diode 14 are connected in series, a diode 15 is connected in parallel with this series circuit in the opposite direction, and the collector of the transistor 16 is connected to the gate G of the power MOS FET 10, the emitter is connected to the anode of the diode 14, and the base Resistor 12 Pulse transformer 6 terminal S
-2 is connected.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This idea is an isolated drive circuit for power MOS FETs that perform switching operations. It is about the road.

0002

[Conventional technology]

An example of a conventional isolated drive circuit of this type is shown in FIG. 2 and will be described. In this figure, 1 is a DC power supply, 2 is a signal source that defines switching time, 3 and 4 are complementary NPN and PNP transistors, 5 is a DC cut capacitor, 6 is a pulse transformer, and P-1, P -2 and S-1, S-2 are the primary and secondary terminals of this pulse transformer 6. 7 is a diode for discharging charges accumulated in the gate capacitance at turn-off, 8 and 9 are gate series resistors and parallel resistors, and 10 is a power MOS FET that performs a switching operation. 11 is the gate input capacitance of this power MOS FET 10. Further, D and G and S ₁ and S ₂ indicate the drain, gate, and source of the power MOS FET 10.

0003 Next, the operation will be explained. When the signal source 2 that defines the switching time goes to “H” level, the NPN transistor The resistor 3 is conductive, and the DC power supply 1 is connected to the DC cut capacitor 5 and the pulse transformer. 6 and the gate series resistor 8 of the power MOS FET 10, and the power MOS Current flows through the gate input capacitor 11, which is the input capacitance between the gate and source of FET 10. This increases the gate-source voltage. Then, when the gate-source voltage exceeds the threshold voltage, the power M OS FET10 is turned on. Conversely, when signal source 2 goes to “L” level, the NPN The transistor 3 becomes non-conductive, and a reverse voltage is generated on the secondary side of the pulse transformer 6. The gate G of the power MOS FET 10 is reverse biased. As a result, the power M The accumulated charge between the gate and source of OS FET10 is released, and the power MOS F ET10 is turned off.

FIG. 3 is a waveform diagram showing the input and output voltage waveforms of the pulse transformer 6, and (a) and (b) show that the pulse width t ₁ when the primary side voltage and the secondary side voltage of the pulse transformer 6 are ON is The voltage waveforms are shown when the voltage waveforms are wide, and (c) and (d) are the voltage waveforms when the pulse width t ₁ when the primary and secondary voltages of the pulse transformer 6 are turned on is narrow. It is something. In FIG. 3, V indicates the primary side voltage of the pulse transformer 6, t ₁ and t ₂ indicate the pulse width when ON and the pulse width when OFF, and T indicates the period. E ₁ and E ₂ represent the secondary voltage of the pulse transformer 6 (period = pulse width t ₁ when ON) and the secondary voltage of the pulse transformer 6 (period = pulse width t ₂ when OFF).

[0005]

[Problem that the idea aims to solve]

Since the conventional power MOS FET isolated drive circuit is configured as described above, the pulse width t ₁ when the primary side voltage of the pulse transformer 6 is turned on is wide, as shown in FIG. 3(a). In this case _{, the} secondary voltage of _the pulse transformer 6 changes as shown in _{FIG .} Since an electromotive force is generated, the gate of the power MOS FET 10 is reverse biased, and the charges accumulated between the gate and source can be rapidly discharged. However, as shown in FIG. 3(c), when the ON pulse width _t1 is very narrow, the generation of back electromotive force is extremely small as shown in FIG. 3(d), and therefore the gate-source There was a problem in that the discharge of charges during the period was delayed, and the turn-off time of the power MOS FET 10 was extended.

[0006] This idea was made to solve this problem, and the pulse width t when ON is ₁ For power MOS FETs that can reverse bias the gate even when the The purpose is to obtain an isolated drive circuit.

[0007]

[Means to solve the problem]

The isolated drive circuit according to this invention is a power MOS that performs switching operation. In the FET drive circuit, a pulse is connected from the source of the above power MOS FET. A capacitor and a first diode are connected in series between the terminals of the transformer. A second diode is connected in the opposite direction in parallel with the series circuit of the capacitor and the first diode. At the same time, connect the collector of the transistor to the gate of the above power MOS FET. , the emitters are connected to the anodes of the first diode, and the transistor Connect the base resistor of the transformer to the terminal of the above pulse transformer, and the above power is applied at turn-off. - Turn-off time is reduced by pulling the gate voltage of the MOS FET to a negative voltage. It is designed to shorten the .

[0008]

[Effect]

In this idea, the capacitor is the input capacitance of the gate of the power MOS FET. The voltage generated in the pulse transformer is divided into capacitances and applied to the capacitor. The voltage is used as a reverse bias voltage, and the transistor operates when the signal source is at “L” level. It operates as a switch to reverse bias the gate of the power MOS FET. , one diode is connected to the power MOS FET when the signal source is at “H” level. The charging current flows to the gate input capacitance and the capacitor, and the other diode is connected to the signal source. When at the "L" level, the energy stored in the pulse transformer is released.

[0009]

【Example】

Figure 1 shows an example of an isolated drive circuit for power MOS FET based on this invention. FIG. In FIG. 1, the same symbols as in FIG. 2 indicate corresponding parts, and 12 is a transistor. 13 is a capacitor for dividing the secondary voltage of the pulse transformer 6. , 14 causes a charging current to flow to the capacitor 13 when the signal source 2 is at the "H" level, and the "L" ” level, a reverse voltage is applied to the diode, causing the transistor to The diode 15 is used to make the signal source 2 conductive when the signal source 2 becomes “L” level. A diode to instantly release the energy stored in the pulse transformer 6, 16 is a switch to reverse bias the gate of power MOS FET10. This is a transistor that operates as follows.

A capacitor 13 and a diode 14 are connected in series between the source S ₁ of the power MOS FET 10 and the terminal S-2 of the pulse transformer 6, and a diode 15 is connected in parallel with the series circuit of the capacitor 13 and the diode 14. At the same time, the collector of the transistor 16 is connected to the gate G of the power MOS FET 10, the emitter is connected to the anode of the diode 14, the base resistor 12 of the transistor 16 is connected to the terminal S-2 of the pulse transformer 6, and the turn-off is performed. The turn-off time is shortened by pulling the gate voltage of the power MOSFET 10 to a negative voltage.

Next, the operation of the embodiment shown in FIG. 1 will be explained. First, when the signal source 2 is at the "H" level, the secondary current of the pulse transformer 6 flows through the route of the resistor 8, the gate input capacitance 11 of the power MOS FET 10, the voltage dividing capacitor 13, and the diode 14, and then passes through the route of the power MOS FET 10. The gate input capacitance 11 and the voltage dividing capacitor 13 are respectively charged to a voltage obtained by dividing the capacitance. Therefore, the anode of the diode 14 has a negative potential with respect to the source S ₁ terminal of the power MOS FET 10.

0012 Next, at the moment when the signal source 2 becomes "L" level, the signal is accumulated in the pulse transformer 6. The energy released is connected to the diode 15 and the gate input of the power MOS FET 10. This is done through a capacitor 11 and a diode 7. At this time, a reverse voltage is applied to the diode 14. In other words, transition The base and emitter of the transistor 16 are forward biased, and this transistor 16 The gate of the power MOS FET 10 is connected to the gate of the diode 14. It is pulled towards the node and is reverse biased. Therefore, the game of power MOS FET10 The charge on the input capacitor 11 will be rapidly discharged. This means that the pulse width This also applies when the reverse voltage generated across the inductance is small. In other words, When signal source 2 is at “H” level, gate input capacitance 11 of power MOS FET 10 and If the voltage dividing capacitor 13 is charged, the signal source 2 will be in trouble when the signal source 2 is at "L" level. This is because the gate can be reverse biased by turning on the transistor 16.

[0013]

[Effect of the idea]

As described above, according to this invention, the capacitor is used as a gate for the power MOS FET. The voltage generated in the pulse transformer is divided by the capacitor input capacitance, and the voltage generated in the pulse transformer is divided into capacitors. Using this voltage as a reverse bias voltage, the transistor As a switch to reverse bias the gate of the power MOS FET when One diode is the power MOS FE when the signal source is at “H” level. The charging current flows to the gate input capacitance of T and the capacitor, and the other diode conducts the signal Releases the energy stored in the pulse transformer when the source is at "L" level This makes it possible to reverse bias the gate even when the pulse width is very narrow. and shorten the turn-off time of power MOS FET compared to conventional ones. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an isolated drive circuit for power MOS FET according to the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional power MOS FET isolated drive circuit.

FIG. 3 is a waveform diagram showing input and output voltage waveforms of the pulse transformer in FIG. 2;

[Explanation of symbols]

2 Signal source 6 Pulse transformer 10 Power MOS FET 12 Base resistance 13 Capacitor 14,15 diode 16 Transistor

Claims (1)

[Scope of utility model registration request] [Claim 1] Power MOS that performs switching operation
In the FET drive circuit, the power MOS F
A capacitor and a first diode are connected in series between the source of the ET and the terminal of the pulse transformer, and a second diode is connected in parallel with the series circuit of the capacitor and the first diode in the opposite direction. The collector is connected to the gate of the power MOS FET, the emitter is connected to the anode of the first diode, the base resistor of the transistor is connected to the terminal of the pulse transformer, and the gate voltage of the power MOS FET is set to negative at turn-off. A power MO characterized by shortening the turn-off time by drawing the voltage.
Isolated drive circuit for S FET.