JPS59121876A - Glass substrate for thin film device - Google Patents
Glass substrate for thin film deviceInfo
- Publication number
- JPS59121876A JPS59121876A JP57227406A JP22740682A JPS59121876A JP S59121876 A JPS59121876 A JP S59121876A JP 57227406 A JP57227406 A JP 57227406A JP 22740682 A JP22740682 A JP 22740682A JP S59121876 A JPS59121876 A JP S59121876A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- thin film
- glass substrate
- film device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 title claims abstract description 46
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 title claims description 28
- 239000005357 flat glass Substances 0.000 claims abstract description 7
- 239000012212 insulator Substances 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract 4
- 229910052681 coesite Inorganic materials 0.000 claims abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract 2
- 239000000377 silicon dioxide Substances 0.000 claims abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract 2
- 229910052682 stishovite Inorganic materials 0.000 claims abstract 2
- 229910052905 tridymite Inorganic materials 0.000 claims abstract 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 101150012845 RHO2 gene Proteins 0.000 claims description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims 2
- 229910005091 Si3N Inorganic materials 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 29
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000035882 stress Effects 0.000 abstract description 6
- 230000008018 melting Effects 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 4
- 230000008646 thermal stress Effects 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 14
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- QCOXXQPKBAIGBQ-UHFFFAOYSA-N 1-hydroxy-2,4,5-trioxa-1-sila-3-aluminabicyclo[1.1.1]pentane Chemical compound O[Si]12O[Al](O1)O2 QCOXXQPKBAIGBQ-UHFFFAOYSA-N 0.000 description 1
- 229910000997 High-speed steel Inorganic materials 0.000 description 1
- 101100001708 Mus musculus Angptl4 gene Proteins 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052916 barium silicate Inorganic materials 0.000 description 1
- HMOQPOVBDRFNIU-UHFFFAOYSA-N barium(2+);dioxido(oxo)silane Chemical compound [Ba+2].[O-][Si]([O-])=O HMOQPOVBDRFNIU-UHFFFAOYSA-N 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、薄膜デバイス用ガラス基板に関する。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a glass substrate for thin film devices.
近年、アモルファスシリコン,ポリシリコン。 In recent years, amorphous silicon and polysilicon.
CdS,CdSe,ZnS等を半導体薄膜として用いる
薄膜トランジスター,誓着センター、太陽電池、エレク
トロルミネッセンスデバイス等の薄FIAfハイスが研
究開発されている。Thin FIAf high speed steels for thin film transistors, bond centers, solar cells, electroluminescence devices, etc. that use CdS, CdSe, ZnS, etc. as semiconductor thin films are being researched and developed.
これらのデバイスは、低価格,太面槓、透光性等の利点
により硼珪酸ガラス等の低融点板ガラスを用いることが
多い。そしてこれらのデバイスの製作には半導体膜形成
、絶縁膜形成,アニール等の比較的高温のプロセスが必
要であり、通常これらのデバイスの製作には複数のマス
クパターンが用いられ,マスク合わせは前のプロセスに
より形成されたパターンと合わせることにより行なわれ
る。しかし上記熱プロセスはガラスの歪点に近い温度で
実行されることが多いため,これらのプロセスによシガ
ラスが変形し,ガラス上に形成したパターンの位置がず
れるため、次のマスクパターンとの調整が不可能になる
という問題点があった。These devices often use low melting point plate glass such as borosilicate glass due to its advantages of low cost, thick surface, light transmittance, and the like. The fabrication of these devices requires relatively high-temperature processes such as semiconductor film formation, insulating film formation, and annealing. Usually, multiple mask patterns are used to fabricate these devices, and mask alignment is performed using the previous mask pattern. This is done by matching the pattern formed by the process. However, since the above thermal processes are often performed at temperatures close to the strain point of the glass, these processes deform the glass and shift the position of the pattern formed on the glass, making it difficult to adjust the pattern with the next mask pattern. The problem was that it became impossible.
これはパターンが高精細な程、又ガラス基板が大口径に
なる程顕著となる。This becomes more noticeable as the pattern becomes more precise and the diameter of the glass substrate becomes larger.
本発明は上述した従来の問題点を解決し、薄膜デバイス
製作時に変形の少ないガラス基板を提供することを目的
とするものである。It is an object of the present invention to solve the above-mentioned conventional problems and to provide a glass substrate that is less deformed during production of thin film devices.
本発明では、低融点板ガラス基板の両面を、一般にはガ
ラスの歪点より十分に低い温度(少なくともガラスの歪
点より150℃以上低い温度)にて、高い歪点を有する
絶縁物により、11tする。ガラスは歪点付近で機械的
応力が急激に弱くなるため、熱応力、機械的応力により
容易に変形するようになるが、両面をガラスの歪点付近
でも機械的強度の強い物質で覆うことにより、基板を強
化し薄膜デバイス作成時の変形が防止される。In the present invention, both sides of a low melting point plate glass substrate are generally heated to 11 t by an insulating material having a high strain point at a temperature sufficiently lower than the strain point of the glass (at least 150 degrees Celsius or more lower than the strain point of the glass). . Since the mechanical stress of glass suddenly weakens near the strain point, it becomes easily deformed by thermal stress and mechanical stress, but by covering both sides with a material that has strong mechanical strength even near the strain point of glass This strengthens the substrate and prevents deformation during production of thin film devices.
絶縁物の被覆温度は、両面同時に被覆し、しかも応力が
かからない状態であれば(例えば取出し時等)更に高い
温度にする事は可能である。しかし一般には上記温度以
下が好ましい。The coating temperature of the insulator can be made higher if both sides are coated at the same time and stress is not applied (for example, during removal). However, in general, temperatures below the above range are preferred.
本発明によれば、たとえガラスの歪点付近の温度におい
ても半導体薄膜の形成、絶縁膜形成、アニールを行なう
ことができ、かつ精確なマスク合わせを行なうことが可
能となる。又、上記工程は一般に高温になる程良好なも
のが得られるため、デバイス特性の改善を図ることがで
きる。更に、基板が大面積になると共にガラスの変形に
よるマスク合わせの困難度は増すため、本発明により大
面積ガラス基板の採用が可能となる。According to the present invention, semiconductor thin films, insulating films, and annealing can be performed even at temperatures near the strain point of glass, and accurate mask alignment can be performed. In addition, since the above process generally yields better results at higher temperatures, it is possible to improve device characteristics. Furthermore, as the area of the substrate becomes larger, the degree of difficulty in mask alignment due to deformation of the glass increases, so the present invention makes it possible to employ a large-area glass substrate.
第1図(a)〜(C)に本発明の実施例を示す。ガラス
基板上にアモルファスシリコンの薄膜トランジスタを形
成した例である。Examples of the present invention are shown in FIGS. 1(a) to (C). This is an example in which an amorphous silicon thin film transistor is formed on a glass substrate.
先ず、コーニング社の、口径4インチ、厚さ0.8調の
7059番の板ガラス11()くリウム硼硅酸ガラス、
歪点593℃)の両面に室温でスノ(ツタ−により5i
0212を片面ずつ1μ堆積した。条件は−Mガス3
mmTorr 、 300 W 、 50分とした。First, Corning Co.'s No. 7059 plate glass with a diameter of 4 inches and a thickness of 0.8 tone,
Strain point: 593°C).
0212 was deposited at 1 μm on each side. The conditions are -M gas 3
mmTorr, 300 W, and 50 minutes.
次いでゲート電極13a、13bとしてM。Next, M is used as the gate electrodes 13a and 13b.
をDCスパッターにより、室温、Arガス、7絽Tor
r、300V、0.2A、10分の条件で約100OA
堆積し、写真食刻技術によりパターン形成を行々った。by DC sputtering at room temperature, Ar gas, 7 Torr
r, 300V, 0.2A, about 100OA for 10 minutes
It was deposited and patterned using photolithographic techniques.
次にゲート絶縁膜としてCVD法により5i0214
f S i H,+02ガスを用い、450℃、常圧、
5分で約300OA堆積した。その後アモルファスシリ
コンをグロー放電分解により、SiH。Next, as a gate insulating film, 5i0214
f S i H, using +02 gas, 450°C, normal pressure,
Approximately 300OA was deposited in 5 minutes. Thereafter, the amorphous silicon was decomposed by glow discharge to form SiH.
ガス、I Torr、 5W 、 40分、基板温度2
80℃の条件で堆積し、パターン形成した(15a、
15b)。Gas, I Torr, 5W, 40 minutes, substrate temperature 2
Deposited at 80°C and patterned (15a,
15b).
この上にΔhを上記した方法で50OAスバツターレ、
AAを150℃で300OA蒸着し、両者をソース・ド
レイン電極16としてパターン形成した。On top of this, Δh is added to 50OA Subatutale by the method described above,
300 OA of AA was deposited at 150° C., and both were patterned as source/drain electrodes 16.
第2図(a)〜(c)に上記工程に対応して示す如く、
両面に5i02#葎層12のない通常のガラス基板では
、ゲー ト絶縁膜の被着工程で凸状に反る。これは、膜
形成後それを室温に戻す途中においてガラスの機械的強
度が弱い為に膨張係数の相違により生じだものと考えら
れる。これに対し本発明ではガラス基板が強化されてい
るので反りが防止される。As shown in FIGS. 2(a) to (c) corresponding to the above steps,
A normal glass substrate without the 5i02# mantle layer 12 on both sides warps into a convex shape during the gate insulating film deposition process. This is thought to be caused by the difference in expansion coefficients due to the weak mechanical strength of the glass during the process of returning it to room temperature after film formation. On the other hand, in the present invention, since the glass substrate is reinforced, warping is prevented.
第3図(al (b)は、上記ウェーハーの端部の互い
に6cm離れた場所1.IIにおけるゲートMo13a
+13bのパターンとアモルファスシリコン15a。FIG. 3(b) shows the gate Mo13a at a location 1.II at the edge of the wafer 6 cm apart from each other.
+13b pattern and amorphous silicon 15a.
15bの合わせパターンを示す。第3図(a)の5in
2被覆の基板では全んどズレが生じていないが、第3図
0))の従来の基板では大きくズしている。第4図(a
l (b)に形成した薄膜トランジスタのパターンを示
す。第4図(b)の従来の薄膜トランジスターでは、パ
ターンずれによりゲートとチャンネルの重なりがなくな
りトランジスターとしての動作が不可能となっている。15b is shown. 5in in Figure 3(a)
Although no misalignment occurs in the two-coat substrate, there is a large misalignment in the conventional substrate shown in FIG. 3 (0)). Figure 4 (a
1(b) shows the pattern of the thin film transistor formed. In the conventional thin film transistor shown in FIG. 4(b), the gate and channel no longer overlap due to pattern misalignment, making it impossible to operate as a transistor.
第5図に上記2種類のガラス基板上に450℃のCVD
法で8102を約3000^堆積した場合の基板の反り
の半径のCVD膜依存性(温度依存性)を示す。実線は
従来法、破線は常温で1μのSi20をスパッター被装
したものである。被覆膜のないものでは第2図[有])
の工程に対応でせると、横軸の400.450,500
℃は、夫々2μ、5μ。Figure 5 shows the 450℃ CVD process on the above two types of glass substrates.
This figure shows the CVD film dependence (temperature dependence) of the radius of warpage of the substrate when approximately 3000^ of 8102 is deposited by the method. The solid line is the conventional method, and the broken line is the sputter coating of 1 μm Si20 at room temperature. For those without a coating film, see Figure 2 [Yes])
If it corresponds to the process of 400,450,500 on the horizontal axis
°C is 2μ and 5μ, respectively.
12μのパターンズレに相当する。これに対し5i02
被覆膜付のガラス基板では反りの半径が3倍以上も大き
くなり、即ち反りが少なくなっている。This corresponds to a pattern deviation of 12μ. On the other hand, 5i02
In the case of a glass substrate with a coating film, the radius of warpage is three times larger or more, that is, the warpage is reduced.
本発明は上記実施例に限られるものではなく、ガラス基
板上のデバイスは密着センサー、太陽電池、エレクトロ
ルミネッセンスデバイス等に適用することが出来る。一
般に絶縁膜のヤング率は大きく変形を生じ易いため、特
に絶縁膜をガラス基板上に形成する時に有用である。又
、ポリシリコンは、500℃程度で通常被着がその場合
にも有効である。又、本発明はアニール時に生じ易い基
板の変形に対しても有効である。又、ガラスの両面に被
覆する膜は、5in2に限らずガラスの歪点以上でも機
械的強度の大きな膜であれば良い。例えばAt20.、
、 ’rho2.Bed、Ti O2,Ta205.
Y2O3、Z r02 、 S IA N4 、 T
aN 、 BN 、 AtN等を使用する事ができる。The present invention is not limited to the above embodiments, and devices on glass substrates can be applied to contact sensors, solar cells, electroluminescence devices, etc. In general, an insulating film has a large Young's modulus and is easily deformed, so it is particularly useful when forming an insulating film on a glass substrate. Furthermore, polysilicon is also effective in cases where it is normally deposited at about 500°C. The present invention is also effective against deformation of the substrate that is likely to occur during annealing. Further, the film to be coated on both sides of the glass is not limited to 5 in 2 and may be any film having a high mechanical strength even above the strain point of the glass. For example, At20. ,
,'rho2. Bed, TiO2, Ta205.
Y2O3, Z r02, S I A N4, T
aN, BN, AtN, etc. can be used.
また、これらの膜の形成方法はスパッターに限らずガラ
スの歪点より十分低い温度で形成できる蒸着、プラズマ
CVD等でもよい。Further, the method for forming these films is not limited to sputtering, but may also be vapor deposition, plasma CVD, etc. which can be formed at a temperature sufficiently lower than the strain point of glass.
又、被膜(被僚膜)の厚さは通常薄膜デバイスに用いら
れる絶縁膜の厚さは数百へ〜1μ、半導体薄膜の厚さは
数千A〜1μであるので被覆膜は少なくとも0.5μ以
上必要である。又、形成時間から10μ以下が好ましい
。即ち、被覆絶縁膜上に形成するガラスの歪点下250
℃又は150℃よシ高い熱工程が加わる絶縁膜や半導体
膜の合計厚さの2倍以上特に3倍以上とするのが本発明
の効果余得る上で好ましい。In addition, the thickness of the coating (covering film) is usually several hundred to 1μ thick for an insulating film used in thin film devices, and the thickness of a semiconductor thin film is several thousand amps to 1μ, so the thickness of the coating film is at least 0.5 μm. .5μ or more is required. Further, from the viewpoint of formation time, the thickness is preferably 10 μm or less. That is, the strain point of the glass formed on the coating insulating film is 250
C. or more than 150.degree. C. It is preferable to set the thickness to at least twice or more, especially at least three times the total thickness of the insulating film or semiconductor film to which a high temperature process of 150.degree.
同、被覆膜の厚さがガラスの両面で異なると、不均等な
応力が発生しガラスの変形が生ずるため、本発明の被覆
膜の厚さはほぼ等しい事が望ましい。Similarly, if the thickness of the coating film is different on both sides of the glass, uneven stress will be generated and the glass will be deformed, so it is desirable that the thickness of the coating film of the present invention be approximately equal.
上記実施例ではバリウム硼硅酸ガラスについて述べたが
、その他アルミ1硅酸ガラスやソーダバリウム硅酸ガラ
ス等の低融点ガラスでも良い。Although barium borosilicate glass was used in the above embodiments, other low melting point glasses such as aluminum monosilicate glass and soda barium silicate glass may be used.
又、被覆絶縁膜はガラスの歪点よりも150℃以上、好
ましくは250℃以上低い温度で被着する事が良い。又
、ガラスの歪点下250℃、特に150℃よシ高い温度
の熱工程が加わる場合に本発明の効果は大きいものであ
る。又、被覆絶縁膜の歪点はガラスの歪点より200℃
以上高くする事が好ましい。Further, the coating insulating film is preferably deposited at a temperature lower than the strain point of the glass by 150° C. or more, preferably 250° C. or more. Further, the effect of the present invention is significant when a thermal process is applied at a temperature higher than 250° C., particularly 150° C., below the strain point of glass. Also, the strain point of the coating insulating film is 200°C lower than the strain point of glass.
It is preferable to make it higher than that.
第1図(a)〜(c)は本発明の詳細な説明する為の断
面図、第2図(a)〜(clは従来例を説明する為の断
面図、第3図(a)(b)及び第4図(a)(b)は夫
々本発明の詳細な説明する為の平面図、第5図は本発明
の詳細な説明する特性図である。
図に於いて、
J】・・・低融点ガラス基板、12・・・5in2膜、
13・・・MOゲート電極、】4・・・cVDsio、
膜、15・・・アモルファスシリコン膜、16・・・ソ
ース・ドレイン用アルミ電極。
代理人 弁理士 則 近 憲 佑(他1名)I]三
↑
プiut 幀6三岳T1
手 続 補 正 書(方式)
1゜ 事件の表示
昭和57年特願第227406号
Z 発明の名称
N Fa テバイス用ガラス基板
3、 補正をする者
事件との関係 特許出願人
(307)東京芝浦電気株式会社
4、 代 理 人
〒100
昭第158年3月29日(発送日)
以上FIGS. 1(a) to (c) are sectional views for explaining the present invention in detail, FIGS. 2(a) to (cl) are sectional views for explaining the conventional example, and FIG. 3(a)( b) and FIGS. 4(a) and 4(b) are respectively plan views for explaining the present invention in detail, and FIG. 5 is a characteristic diagram for explaining the present invention in detail. ...Low melting point glass substrate, 12...5in2 film,
13...MO gate electrode, ]4...cVDsio,
Film, 15... Amorphous silicon film, 16... Aluminum electrode for source/drain. Agent Patent attorney Kensuke Chika (and 1 other person) Glass Substrates for Devices 3, Relationship with the Amended Person Case Patent Applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent 100 March 29, 1973 (shipment date) Above
Claims (1)
点より高い歪点を持つ絶縁物により被覆されて成る事を
特徴とする薄膜デバイス用ガラス基板。 (2) 絶縁物が板ガラスの歪点よ9150℃以上低
温で形成されている事を特徴とする特許求の範囲第1項
記載の薄膜デバイス用ガラス基板。 (3) 絶縁物の歪点が板ガラスの歪点よ9200℃
以上高い事を特徴とする前記特許請求の範囲第1項記載
の薄膜デバイス用ガラス基板。 (4) 絶縁物としてS i O2, AA20,
、 ’rho2, Bed。 TiO2,Ta20, 、 Y2O, 、 ZrO2,
Si3N, 、 TaN。 BN又はAlNを用いた事を特徴とする前記特許請求の
範囲第1項記載の薄膜デバイス用ガラス基板。 (5)絶縁物の厚さが0. 5〜10μである事を特徴
とする前記特許請求の範囲第1項記載の薄膜デバイス用
カラス基板、9[Scope of Claims] fil A glass substrate for a thin film device, characterized in that both sides of a low-melting point glass plate are covered with an insulator having a strain point higher than that of the plate glass. (2) A glass substrate for a thin film device according to claim 1, wherein the insulator is formed at a temperature that is 9150° C. or lower than the strain point of the plate glass. (3) The strain point of the insulator is 9200°C higher than that of plate glass.
The glass substrate for a thin film device according to claim 1, characterized in that the glass substrate is higher than or equal to 100%. (4) As an insulator, SiO2, AA20,
, 'rho2, Bed. TiO2, Ta20, , Y2O, , ZrO2,
Si3N, , TaN. The glass substrate for a thin film device according to claim 1, characterized in that BN or AlN is used. (5) The thickness of the insulator is 0. The glass substrate for a thin film device according to claim 1, characterized in that it has a thickness of 5 to 10μ.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57227406A JPS59121876A (en) | 1982-12-28 | 1982-12-28 | Glass substrate for thin film device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57227406A JPS59121876A (en) | 1982-12-28 | 1982-12-28 | Glass substrate for thin film device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59121876A true JPS59121876A (en) | 1984-07-14 |
Family
ID=16860328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57227406A Pending JPS59121876A (en) | 1982-12-28 | 1982-12-28 | Glass substrate for thin film device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59121876A (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6270817A (en) * | 1985-08-02 | 1987-04-01 | ゼネラル・エレクトリツク・カンパニイ | Structure and method for manufacturing for thin film field effect transistor matrix address type liquid crystal displayunit |
JPS6272167A (en) * | 1985-08-02 | 1987-04-02 | ゼネラル・エレクトリツク・カンパニイ | Depositing and curing method for gate electrode material forthin film field effect transistor |
JPH02260570A (en) * | 1988-12-24 | 1990-10-23 | Samsung Electron Devices Co Ltd | Polycrystalline silicon film transistor |
JPH02275622A (en) * | 1989-04-17 | 1990-11-09 | Sony Corp | Annealing method |
JPH05251707A (en) * | 1992-03-04 | 1993-09-28 | Koudo Eizou Gijutsu Kenkyusho:Kk | Thin-film transistor and its manufacture |
JPH06296023A (en) * | 1993-02-10 | 1994-10-21 | Semiconductor Energy Lab Co Ltd | Thin-film semiconductor device and manufacture thereof |
US5929487A (en) * | 1993-10-12 | 1999-07-27 | Semiconductor Energy Laboratory Co., Ltd. | Glass substrate assembly, semiconductor device and method of heat-treating glass substrate |
US5946561A (en) * | 1991-03-18 | 1999-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
KR20000038714A (en) * | 1998-12-08 | 2000-07-05 | 윤종용 | Method for manufacturing liquid crystal display |
US6534832B2 (en) | 1993-09-07 | 2003-03-18 | Semiconductor Energy Laboratory Co., Ltd. | Display device and glass member and substrate member having film comprising aluminum, nitrogen and oxygen |
US6624450B1 (en) | 1992-03-27 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
US6680488B2 (en) | 2001-04-20 | 2004-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US6964890B1 (en) | 1992-03-17 | 2005-11-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54159243A (en) * | 1978-06-07 | 1979-12-15 | Hitachi Ltd | Liquid crystal dispaly device |
-
1982
- 1982-12-28 JP JP57227406A patent/JPS59121876A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54159243A (en) * | 1978-06-07 | 1979-12-15 | Hitachi Ltd | Liquid crystal dispaly device |
Cited By (36)
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---|---|---|---|---|
JPS6272167A (en) * | 1985-08-02 | 1987-04-02 | ゼネラル・エレクトリツク・カンパニイ | Depositing and curing method for gate electrode material forthin film field effect transistor |
JPS6270817A (en) * | 1985-08-02 | 1987-04-01 | ゼネラル・エレクトリツク・カンパニイ | Structure and method for manufacturing for thin film field effect transistor matrix address type liquid crystal displayunit |
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