JPS59119949A - Signal transmission and reception method - Google Patents

Abstract

PURPOSE:To obtain a correct data signal in a short time by converting the data signal of a binary value into the pulse having same width with the same data signal and the pulse having different width with the different data signal respectively. CONSTITUTION:A parallel data given from outside is fetched to a data register 1 to hold and transferred to a transmission register 3 at the first time point when the external parallel data is converted into a serial data. A timing circuit 2 gives timing to a start signal producing circuit 4 later on, and the circuit 4 transfers the start signal with said timing to a gate driver circuit 10 in the form of a serial train in response to the time of a transmission clock 9 to output externally. The circuit 2 gives timing to the register 3 after the start signal is transmitted to send a piece of data within the register to a 0/1 deciding circuit 6.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for transmitting and receiving signals, and particularly to a method for quickly obtaining a correct data signal by correcting a data signal [Prior art] ] Conventional signal transmission devices transmit data into data signals rOJ, r
When transmitting instead of lJ, one pulse is used to represent rOJ or "1", and during that pulse [OJ, r
There are two methods: one method is to change the number of pulses according to lJ, and the other is to use a plurality of the same pulses and change rOJ or "1" to change the number of pulses. In the former method, if the pulse waveform deviates due to disturbance or the like during or after transmission, the only pulse deviates by 4, and all normal pulses disappear, making it impossible to correct the data signal correctly. In the latter case, even if a small number of pulses are distorted, it will be difficult to distinguish between the data and it will cause a large numerical difference in the number of pulses representing each data, so it will be necessary to test a large number of pulses, and the transmission and reception will be difficult. The disadvantage was that it took a long time.

[Purpose of the invention]

An object of the present invention is to provide a signal transmission method that can obtain correct data signals in a short time.

[Summary of the invention]

The present invention provides a method for transmitting and receiving data signals "0" and "1" by converting them into pulses.
The data signal "1" is changed into a pulse train consisting of two or more pulses in the pulse train, and the data signal "1" is transmitted as a pulse train consisting of two or more pulses in the pulse train.
The number of pulses included in the received pulse train is counted, and the pulse width of the pulse forming the data signal "O" is determined to be among the received pulse examples. If the received pulse train is present in the data signal "0", the received pulse train is verified as the data signal "0", and the data signal "0" is detected.
If a pulse with a width of 1" exists in the received pulse example, the received pulse train is
This signal transmission/reception method is characterized by verifying that the signal is ``1''.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 shows a transmitting circuit in this signal transmitting device. Data register 1 is the 1? of data register 1 that captures and holds parallel data from the outside. The contents of data register 1 are transferred to transmission register 3 for serial transmission of the data. The timing of transfer is given by the timing circuit 2 at the beginning of converting external parallel data into serial data. When the timing circuit 2 transfers the contents of the data register 1 to the transmission register 3, it provides timing to the start signal generation circuit 4.

At this timing, the start signal generation circuit 4 transfers the start signal n to the gate driver circuit 10 as a serial string according to the time of the transmission clock 9, and outputs it to the outside. After the start signal n is sent out, the timing circuit 2 gives timing to the transmission register 3 and sends one piece of data in the register to the rob/rlJ determination circuit 6. Second
The figure shows an example of data in the transmission register 3.

The transmission register 3 receives timing signals from the timing circuit 2, for example, in this example, from the right, the signals are 1'-0-41→...→1-〇-1-1. [og, rlJ determination circuit 6.

The OJ, rlJ determination circuit 6 activates the rOJ code creation circuit 7 in the subsequent stage depending on whether one piece of data sent from the transmission register 3 is 0 or 1.If the sound is "1", the code creation circuit 8 is activated. . The "0" code generation circuit 7 or the "1" code generation circuit 8 receives the timing signal from the timing circuit 2, generates a pulse train as shown in FIG. and externally as a serial string.

When the data of the I BiT in the transmission register 3 is sent out as described above, the timing circuit 2 outputs the next I BiT in the transmission register 3 as described above [OJ, rlJ determination circuit 6
The data is output to the outside as a serial string one after another.

When all the data in the transmission register is output, the timing circuit 2 activates the end signal generation circuit 5 and causes the end signal generation circuit 5 to output an end signal according to the time of the transmission clock.

Through the above procedure, the parallel data in the data register I and the gate-driver circuit 10 transmit the signal as a serial signal.

Next, a mechanism for determining the quality of data and correcting errors using a small number of pulses, which is a feature of the present invention, will be explained using FIGS. 3 to 6.

As explained in connection with the transmitter in FIG. 1, an example signal as shown in FIG. 6 is transmitted to the receiver. In Figure 6, n
indicates a start signal, 23 indicates data, and U indicates an end signal.

In FIG. 3, the start detection circuit 12 detects that the beginning of the serial signal is a start signal, and activates the interval timing circuit 15.

The interval timing circuit 15 provides the timing for taking in the rOJ and rlJ pulse trains that come in at regular intervals. "0" sign check circuit 13, and "
1'' code check circuit 14 receives the reception clock 5 and receives the received clock 5.
Check whether the code is 0" or 11". That is, in FIG. 4, if the IBiT data has a code of 10, it is checked whether pulse 1] is T and the rest period is T, and these pulses are a train of three. Similarly, if the I BIT data is a code of "1", it is checked that the pulse is at Tt, the pause period is at T1, and the number of pulses is three. Next, for example, the 0 data verification circuit 16 checks that the pulse train checked by the "0" code check circuit 13 is processed by the reception code (11, +21 in FIG. (If there is a deviation, the pulse width of two of the three pulses is T, and if it is normal and received within the specified time, based on the output information from the check circuit.
The "0" data verification circuit 16 verifies the received data as "10" and certifies the data as correct.

Similarly, when the received data is "11", the "1" sign check circuit 14 checks T! Count the number of pulses in time and use the result as
1'' data verification circuit 17 determines whether the data is 11'' or incorrect data.

When each verification circuit determines that the data is correct, the respective data "0" and data "1" are set in the data register 21. The data register 4 captures and parallelizes these signals in accordance with the timing signal generated by the interval timing circuit.

For example, if the data is neither "0" nor "1" in the "0" data verification circuit 16 and "1" data verification circuit 17, the error detection circuit is
, When the number of pulses during time T2 does not exist in the pulse train, an error is detected as incorrect data that cannot be corrected, and the data register 21 is reset from the error detection circuit (a).

As described above, according to this embodiment, data errors are detected and corrected using a train of three pulses for IBiT data, and the data can be transmitted in a short time.

〔Effect of the invention〕

As described above, according to the present invention, even if a pulse train is missing due to noise during the pulse train, it is possible to confirm that a normal number of pulses that have not been lost are still present in the received pulse train. Since it is possible to check and verify the type of data replaced with a pulse train and recognize it as the same correct data as the source, it is possible to perform correct data recognition compared to transmitting a single pulse with a different pulse width. This has the effect of reducing the number of errors and increasing the recognition speed compared to transmitting each data with a large numerical difference in the number of single pulses in the pulse train.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmitter of a signal transmission device according to an embodiment of the present invention, FIG. 2 is an example of data in the transmission register of FIG. 1, and FIG. 3 is a block diagram of a transmitter of a signal transmission device according to an embodiment of the present invention. 4 is an explanatory diagram of a pulse train adopted in an embodiment of the present invention; FIG. 5 is a diagram of a pulse missing state of the pulse train with code "0" shown in FIG. 4; and FIG. 6 is a block diagram of a receiver. , is a configuration diagram of an example of transmitted and received data in an embodiment of the present invention. l...Data register, 2...Timing circuit, 3...Transmission register, 4...
- Start signal creation circuit, 5... End signal creation circuit, 6... "0".

Claims (1)

[Claims] 1. In a method of transmitting and receiving data signals "0" and "1" by converting them into pulses, the data signal "0" is changed into a pulse train consisting of two or more identical pulses and transmitted, and the data signal Transmitting "1" by changing it into a pulse train consisting of two or more identical pulses different from the pulse train, and counting the number of pulses in the middle included in the received pulse train,
If a pulse having the width of the pulse forming the data signal rOJ is present in the received pulse example, the received pulse train is verified as the data signal "0", and the data signal rOJ is verified as the data signal "1".
If a pulse with a pulse width of
A signal transmission and reception method characterized by verifying that