JPS59117124A - Formation of wiring pattern - Google Patents
Formation of wiring patternInfo
- Publication number
- JPS59117124A JPS59117124A JP22583182A JP22583182A JPS59117124A JP S59117124 A JPS59117124 A JP S59117124A JP 22583182 A JP22583182 A JP 22583182A JP 22583182 A JP22583182 A JP 22583182A JP S59117124 A JPS59117124 A JP S59117124A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- metal
- resist
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- NPEWZDADCAZMNF-UHFFFAOYSA-N gold iron Chemical compound [Fe].[Au] NPEWZDADCAZMNF-UHFFFAOYSA-N 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 22
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010884 ion-beam technique Methods 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 239000002344 surface layer Substances 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 206010011732 Cyst Diseases 0.000 description 2
- 208000031513 cyst Diseases 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 101100536577 Caenorhabditis elegans cct-4 gene Proteins 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- -1 Oxygen ions Chemical class 0.000 description 1
- 241001474791 Proboscis Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は配線パターンの形成方法ｒ（関するものであシ
、特に記録層を選択的に配化して、得られた該酸化層を
マスクとしてエツチングし配線パターンを形成する方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for forming a wiring pattern (in particular, a method for selectively disposing a recording layer and using the obtained oxide layer as a mask). This invention relates to a method of etching to form a wiring pattern.
（２）技術の背双
一般的に、半尋体基板（ウェー・）全曲に例涜された一
極材別を込択的に除去してｂ１望の配線パターン全形成
する時は、該電極伺相面に選択的にマスクを抜法し、化
学薬品中で除去するウェットエツチング法又はガスグラ
ダマ中で除去するドライエツチング法が用いられる。(2) Technological background Generally speaking, when forming the entire wiring pattern of B1 by selectively removing the unipolar material that has been removed from the entire half-width board, the electrode A wet etching method is used in which the mask is selectively removed from the exposed surface and removed in a chemical agent, or a dry etching method is used in which the mask is removed in a gas gradation bath.
（３）従来技術と問題点
従来、好感度なネガレノストをマスク材料として配線パ
ターンを形成しようとした砲台、２ンよいし３．５ミク
ロン程度の解像性がが限界でり９、それ以上、例えは１
．５ミクロン柱度の解１ｐ性は得られなかった。このよ
うなネガレジストを用いては得られない微細パターンを
形成するに（は、解像性の良い７ぎジレノストを用いれ
は侑ることが出来る。(3) Prior art and problems In the past, attempts were made to form wiring patterns using the highly sensitive negative electrode mask material, but the resolution was limited to about 2 or 3.5 microns9; Example is 1
．． A solution 1p property of 5 micron columnarity was not obtained. To form a fine pattern that cannot be obtained using such a negative resist, it is possible to use a 7-degree resist with good resolution.
又１μないしはツブミクロン領域では電子線露光等が用
いられる。この場合でもネがｌ／シストよシボジレノス
トの解像性がより優れている。Further, in the 1 μm or submicron region, electron beam exposure or the like is used. Even in this case, the resolution of Shibojirenost is better than that of Nega1/Cyst.
（４）発明の目的
本発明は上記のように解像性の優れたポジレジストを用
いて微細な配蔵パターンを提供しようとするものでメジ
、特に耐ドライエ１．テング注に劣る↑Ｌ子紗用ボルノ
ストを用いて微細配線を形成するのに不動である。(4) Purpose of the Invention The present invention aims to provide a fine pattern using a positive resist with excellent resolution as described above. It is difficult to form fine wiring using ↑L bornost, which is inferior to proboscis.
（５）発明のに成
不発り」の目的は半導体基板上に金属（配線）層を形成
し、眩毎１１）（配線）層」二にレジストお松属し、次
に露光し、８１ｉ！曹することによって微細なＬ・シス
トパターンを形成し、次に該レジストのノやターニング
によって露出した金ス・鳴Ｊ會入ｍ」に岐累イオンビー
ム足照射して酸化せしめることにより、該金槌表向層を
該金后５の１１夕化股層に友化せしめ、該酸化膜層をマ
スクとしてドライエツチングすることを特徴とするＦ”
ｊｊＬ線パターンのりしＱ’７方伝によって達成される
。(5) The purpose of "Invention Success or Failure" is to form a metal (wiring) layer on a semiconductor substrate, apply a resist to the second (11) (wiring) layer, and then expose it to 81i! A fine L/cyst pattern is formed by drilling, and then the metal layer exposed by turning and turning the resist is irradiated with a cumulative ion beam to oxidize it. F" characterized in that the surface layer is made to be compatible with the oxide film layer, and dry etching is performed using the oxide film layer as a mask.
This is achieved by applying the jjL line pattern to the Q'7 direction.
すなわち本発明で（ｄレノストん１を配線パターン形成
のマスク材料とぜす、単に飼細なレジスト・？ターンを
形ｊ或し、そのパターンによって形成された館（惹）を
利用するものであって、血出され１こ半導体基板上の金
属配線層を該レジン） ｉ９ターンの溝を介して酸化し
、生成された酸化膜層をマスクとしてドライエツチング
することによって自己線パターンを形成するのである。In other words, in the present invention, (by using d-renostone 1 as a mask material for forming a wiring pattern, simply forming a detailed resist pattern or using a hole formed by the pattern). Then, the metal wiring layer on the semiconductor substrate is oxidized through the groove of the resin (i9), and a self-line pattern is formed by dry etching using the generated oxide film layer as a mask. .
本発明において使用するレノストはポジレジストである
のが微細な配線・ぐターンを形成するフこめに好丑しい
。It is preferable that the resist used in the present invention be a positive resist for forming fine wiring and patterns.
更に本発明におけるドライエツチングとして、プラズマ
エツチング待（・′こ対Ｖ別１ａ紘全由い７こリアクテ
ィブイオンエツチングか好暫しい。Furthermore, as the dry etching in the present invention, plasma etching (reactive ion etching) is preferable.
（６）発りｊ」の実施例
」以下木ジらヴ」の実施例を図１１」に基ついて説明す
る。(6) Example of ``Departure j'' An example of ``Kijirav'' will be described based on ``FIG. 11''.
第１図から第５１迄は本さ、：ｌ明に係る１つの東ｂｉ
例を説す］する／ζめの概略工程断面図である・シリコ
ンシ＾板１上にアルミニウム（Ａ’／−）金属層２を約
１ミクロンの）♀みに蒸膚−せしめ、該Ａｔ金属層２上
に例えはｐｒＡＭＡ（ポリメチルメタリソレート）のボ
ッレノスト３をスピンコード法によ’ｎ塗布ｆる。かか
る状態を第１図に示す。Figures 1 to 51 are books: one eastern bibliography related to the Ming Dynasty.
This is a schematic cross-sectional view of the process for / Bollenost 3 made of prAMA (polymethyl metaresolate), for example, is applied onto layer 2 by a spin-coating method. Such a state is shown in FIG.
次にし、月？ジレジヌト３を１８子線露光技術によって
約０．５ミクロンのラインアンドスペースのレジストパ
ターンを札゛た。かかる状態を第２図に示す。Next month? A resist pattern of approximately 0.5 micron lines and spaces was printed on GIRENUT 3 using 18-ray exposure technology. Such a state is shown in FIG.
なお第２１Ｚｌ中にライン及びスペースをそ几ぞれＬ及
びＳで示ず・
次に・１り〕られたレノストパターンの７４−ス（ｒｌ
’＋Ｅ＋ ） ＊介して蕗出し／ヒＡｔ金属層表面２′
に酸素イオン（φ［４２図Ａ）をイオン注入によって打
ち込む。Note that the lines and spaces in the 21st Zl are not indicated by L and S respectively.
'+E+)
Oxygen ions (φ [Fig. 42A)] are implanted into the wafer by ion implantation.
その力１１速電圧は初め１ＱｋｅＶ次に４ＱｋｅＶの２
段階で１丁ないドーズ量はそれぞれ１ｏ １７ 、＋駆
−２で行なっグヒ。その結果、Ａｔの酸化膜４の厚さは
約１０００〜１５００Ｘ程度になった。かかる状態を第
３図に示す。The force 11 speed voltage is initially 1QkeV and then 2QkeV of 4QkeV.
The doses that are not enough at each stage are 1o 17 and +K -2, respectively. As a result, the thickness of the At oxide film 4 was approximately 1000 to 1500X. Such a state is shown in FIG.
次に第３図に示さｔたレノスト３をプラズマアッシング
によって除去する。かかる状態を第４図に示す。Next, the renost 3 shown in FIG. 3 is removed by plasma ashing. Such a state is shown in FIG.
次に第３図において形成されたＡ７の酸化膜４をマスク
にしそして四塩化炭素（ＣＣｔ４）ガスをエッチャント
としてＡｔ金属層２をプラズマエツチングによって除去
する。グラズマエッテング処理の条件としてはガス圧０
．１トール、′電力５００ Ｗで約１０分間行ない、約
１μｍの厚みのＡｔ金属層をパターニングせしめ、Ａｔ
配線パターン２ａを形成した。かかる状態を第５図に示
す。Next, the At metal layer 2 is removed by plasma etching using the A7 oxide film 4 formed in FIG. 3 as a mask and using carbon tetrachloride (CCt4) gas as an etchant. The conditions for glazma etching treatment are gas pressure 0.
．． 1 torr and a power of 500 W for about 10 minutes to pattern an At metal layer with a thickness of about 1 μm.
A wiring pattern 2a was formed. Such a state is shown in FIG.
本実施例において解像性の良いボッレノストヲ用いてい
るのでその解像性をその丑ま金属配線パターンに応用可
能である。本実施例のアルミニウムその他モリブデン、
タングステン、等の金属配線を形成する種々の金属は酸
化せしめられるとプラズマエツチング、リブクティブイ
オンスパｙタエッチング等のドライエッチングレートカ
樋’＋ １１５〜１／２０と低下するので酸化されてい
ない金属層が先にエツチングされ、酸化膜形成された金
属層が残存することになる。このよう（（シて閂己線パ
タ−ン力〕形成される。In this embodiment, since a bolt having good resolution is used, the resolution can be applied to the metal wiring pattern. Aluminum and molybdenum of this example,
When various metals forming metal wiring, such as tungsten, are oxidized, the dry etching rate of plasma etching, revactive ion sputter etching, etc. decreases to +115 to 1/20; therefore, unoxidized metals The layers are etched first, leaving behind an oxidized metal layer. This is how the line pattern is formed.
（７）発明の効果
以上の祝（刀から本発明によれはポジレジストを用いで
、又レノストの面１エツチング性を考慮せずに微細７２
：配線パターンを形成することが出来る。(7) Congratulations beyond the effects of the invention (from the sword, according to the present invention, a positive resist was used, and fine 72 mm was etched without taking into account the etching properties of Lennost's surface 1).
: Wiring patterns can be formed.
４Ｉλイ１面の１．・１０１′（な説明第１図から第５
１迄は本発明に係る１つの実施例を説明するための仏を
略工程１（シ１面図である。4IλA 1st page.・101' (explanation from Figures 1 to 5)
1 to 1 are schematic views showing step 1 (FIG. 1) for explaining one embodiment of the present invention.
■・・・シリコン基板、２・・・Ａ７金属層、２ａ・・
・Ａｔ配線パターン、２′・・・露出したＡ、ａ金属）
會衣面、３・・・７」？ルノスト、４・・・Ａ７の酸化
膜。■...Silicon substrate, 2...A7 metal layer, 2a...
・At wiring pattern, 2'...exposed A, a metal)
Meeting face, 3...7''? Lunost, 4...A7 oxide film.
・侍許出願人
富士辿株式会社
竹１ｉｆ−出ル１１代乃１人
弁理± １ｔ 木 朗
弁、１．！ｌＩ１士 西 鵠 和 之弁理士
内 １） 幸 男
−ｆｆＪψ士 山 口 昭 ２第１図
第３図・Samurai license applicant Fujitori Co., Ltd. Take 1if-Deru 11th generation attorney ± 1t Ki Roben, 1. ! 1st Patent Attorney Kazuyuki Nishi
1) Yukio-ffJψshi Yamaguchi Akira 2 Figure 1 Figure 3
Claims (1)
該金Ｊｔ・（でｌ′Ｉ１．′縁）層上に１７ノストを被
着し、次に露光し、現ｉ＝’ することによって微細な
レジストパターンケ形欣し、次に該レノストのパターニ
ングによっでｊ、・１−出した全組）’ｊＪ秋而に面素
イオンを照射してｊ１ン化せしめることにより酸化膜層
を形成し、該１）支化Ｉｉ、’、ｌ冒をマスクとしてド
ライエツチングすることを４」仏とする配線ノぐターン
のノし取方法。 ２− ｉｊ！Ｊ ｆｆ１Ｌニレジストとしてポジレジ
ストを１更用することをｑ１旬ｔとするｌ清ｆｒ＃Ｎｊ
求の争巳囲訝Ｌ１項ｄ己鴨のカフ２＜〇 ’ ｌ」！」ｉピｊ４ｒＬ出した金Ｊ’：４層オ七面
の数比２、歌集イオンをｍ ｕ（２金シゴ）表面に打ち
込むことによって行なうことを特徴とする特♂ｆ’Ｂｒ
ｉ求の範囲第１項記載の方法。 ４− ＨｔＪｉｊ已ドライニドライエツチングズマエ
２．チングによって行なうことを特徴とする特許請求の
範囲第１項記載の方法。[Claims] 1. Forming metal (wiring pattern) on the substrate,
17 Nost is deposited on the gold Jt (and l'I1.' edge) layer, and then exposed to light to form a fine resist pattern, and then patterned. Therefore, an oxide film layer is formed by irradiating surface element ions on j,・1−) 'jJ autumn to form an oxide film layer, and 4. A method for cutting out wiring turns using dry etching as a mask. 2-ij! J ff1L clearing fr#Nj where it is assumed that one change of positive resist is used as the second resist.
Seeking conflict L1 term d self-duck cuff 2<〇'l''! ``ipi j4rL gold J': 4 layer O7 surface number ratio 2, a special feature that is performed by driving ion into the surface of mu (2 gold iron) ♂f'Br
The method described in item 1 of the scope of i-required. 4- HtJij's dry etchings 2. The method according to claim 1, characterized in that the method is carried out by chiming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22583182A JPS59117124A (en) | 1982-12-24 | 1982-12-24 | Formation of wiring pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22583182A JPS59117124A (en) | 1982-12-24 | 1982-12-24 | Formation of wiring pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59117124A true JPS59117124A (en) | 1984-07-06 |
Family
ID=16835488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22583182A Pending JPS59117124A (en) | 1982-12-24 | 1982-12-24 | Formation of wiring pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117124A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112534341A (en) * | 2018-07-31 | 2021-03-19 | 豪雅镜片泰国有限公司 | Optical product and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5496370A (en) * | 1978-01-13 | 1979-07-30 | Mitsubishi Electric Corp | Mask forming method |
| JPS563679A (en) * | 1979-06-22 | 1981-01-14 | Mitsubishi Electric Corp | Formation of metallic pattern |
-
1982
- 1982-12-24 JP JP22583182A patent/JPS59117124A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5496370A (en) * | 1978-01-13 | 1979-07-30 | Mitsubishi Electric Corp | Mask forming method |
| JPS563679A (en) * | 1979-06-22 | 1981-01-14 | Mitsubishi Electric Corp | Formation of metallic pattern |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112534341A (en) * | 2018-07-31 | 2021-03-19 | 豪雅镜片泰国有限公司 | Optical product and method for manufacturing the same |
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