JPS59116999A - Memory destruction verifying system - Google Patents
Memory destruction verifying systemInfo
- Publication number
- JPS59116999A JPS59116999A JP57223743A JP22374382A JPS59116999A JP S59116999 A JPS59116999 A JP S59116999A JP 57223743 A JP57223743 A JP 57223743A JP 22374382 A JP22374382 A JP 22374382A JP S59116999 A JPS59116999 A JP S59116999A
- Authority
- JP
- Japan
- Prior art keywords
- crc code
- data
- main memory
- destruction
- crc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、主記憶装置とサイクリック(以下CRCと称
する)符号生成装置を有するシステムータ等が正常であ
るという保障がない場合、一般に、バックアップ用の補
助記憶装置(例として、マグネティックテープ、磁気ド
ラム装置等)からプログラム、データを主記憶装置に再
転送するのが普通である。しかし、大量のデータ転送や
入出力装置の処理速度が遅い場合は、その転送時間が大
きくなシ、システムの連続性に犬−夕に破壊があるかど
うかを速やかに判定する式に基づき、 CRC符号生成
装置を用いて、主記憶装置のプログラムやデータの破−
壊を検証可能第1図は、本発明を適用したシステム例の
構成を示すブロック図である。それぞれの装置は、中央
制御装置+ 、CRC符号生成装置2.主記憶装置5、
補助記憶装置4である。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is generally applicable to a backup system when there is no guarantee that a system router having a main memory and a cyclic (hereinafter referred to as CRC) code generating device is normal. Normally, programs and data are retransferred from an auxiliary storage device (for example, a magnetic tape, a magnetic drum device, etc.) to the main storage device. However, if a large amount of data is transferred or the processing speed of the input/output device is slow, the transfer time is large, and the CRC is used to quickly determine whether there is any disruption to the continuity of the system. Destruction of programs and data in main memory using a code generator
FIG. 1 is a block diagram showing the configuration of an example system to which the present invention is applied. Each device includes a central controller +, a CRC code generator 2. main storage device 5;
This is an auxiliary storage device 4.
初期プログラムロード時、中央制御装置1は補助記憶装
置2に格納されているプログラムやデータ類を主記憶装
置5へ転送させる。その後、CRC符号生成装置2に対
して、 CRC符号を生成すべき内容不変のプr、ダラ
ムやデータ類の開始アドレスとサイズな入力として、
CRC符号生成を指令する。CRC生成符号装置2け上
記指令に基づきCRC符号を生成且つ記憶しておく。At the time of initial program loading, the central control device 1 causes the programs and data stored in the auxiliary storage device 2 to be transferred to the main storage device 5. After that, inputs to the CRC code generation device 2, such as the start address and size of the unchanging program, duram, and data for which the CRC code is to be generated, are input.
Commands CRC code generation. The CRC generation code device 2 generates and stores a CRC code based on the above instructions.
第2図は、 CRC符号生成装置2の詳細構成例を示す
もので、データのリードあるいはライトを制御するり一
ド/ライト制御部21、主記憶上のCRC符号生成対象
のプログラムやデータ類のアドレスを記憶しておくアド
レスポインタ部26、アドレス更新を行うアドレス演算
部22、CRC符号を生成且つ記憶(7てお(’ CR
C符号生成記憶部24から構成される。すなわち、中央
制御装置1よりCRC符号生成対象の主記憶装置5上の
開始アドレスとサイズが、リード/ライト制御部21へ
指定される。リード/ライト制御部21は開始アドレス
とサイズをアドレスポインタ部25.アドレス演算部2
2へ指示する。そして、アドレスポインタ部で指定され
るアドレスの内容に対してCRC符号生成記憶部24で
CRC符号を生成しその結果を記憶する。またアドレス
演算部22は、アドレスを+1だけ更新し、サイズを越
えたかどうかチェックする。すなわち、上記動作をサイ
ズ分だけくシかえし、CRC符号生成記憶することにな
る。また、中央i制御装置1は必要なときにリード/ラ
イト制御部21へCRC符号の読み取りを指令すること
ができる。FIG. 2 shows a detailed configuration example of the CRC code generation device 2, which includes a read/write control section 21 that controls reading or writing of data, and a program and data type for CRC code generation in the main memory. The address pointer unit 26 stores addresses, the address calculation unit 22 updates addresses, and generates and stores CRC codes (7 and (' CR
It is composed of a C code generation storage section 24. That is, the central control unit 1 specifies the start address and size on the main storage device 5 of which the CRC code is to be generated to the read/write control unit 21 . The read/write control unit 21 stores the start address and size in the address pointer unit 25. Address calculation section 2
Instruct to 2. Then, the CRC code generation storage unit 24 generates a CRC code for the contents of the address specified by the address pointer unit, and stores the result. Further, the address calculation unit 22 updates the address by +1 and checks whether the size has been exceeded. That is, the above operation is repeated by the size, and the CRC code is generated and stored. Further, the central i-control device 1 can instruct the read/write control section 21 to read the CRC code when necessary.
そこで、主記憶装置3に格納された内容不変のプログラ
ムやデータ類が破壊されているかどうかチェックする必
要がある時、中央制御装置1は、再度、同一の開始アド
レスとサイズを入力データとしてCRC符号生成装置2
に対して与え、CRC符号生成を指示する。そして、そ
のrx。Therefore, when it is necessary to check whether programs and data whose contents remain unchanged stored in the main memory device 3 have been destroyed, the central control device 1 again inputs the same start address and size as input data and converts them into CRC codes. Generation device 2
and instructs CRC code generation. And that rx.
符号とあらかじめ初期プコグラムロード時に生成してお
いた結果とを照合し、一致していればメモリ破壊がない
と判定し、プログラムやデータ類を主起憶装り5へ再転
送しない。不一致の場合は、メモリ破壊があると判定し
、補助記憶装置4から主記憶装置5ヘプログラムやデー
タの判定手段を与えることで、メモリ破壊の可能性があ
るだけで補助記憶装置から主記憶装置へプログラムやデ
ータを再転送していた場合をメモリ破壊があるときのみ
に限定でき、システムの中断時間を少なくする効果があ
る。The code is compared with the result generated in advance at the time of initial pcogram loading, and if they match, it is determined that there is no memory corruption, and the program and data are not transferred to the main memory 5 again. If there is a mismatch, it is determined that there is memory corruption, and by providing a means of determining programs and data from the auxiliary storage device 4 to the main storage device 5, the auxiliary storage device is transferred from the main storage device even if there is a possibility of memory corruption. It is possible to limit the retransfer of programs and data to only when there is memory corruption, which has the effect of reducing system interruption time.
第1図は本発明の一英前例のシステムのブロック図、第
2図は同じ(CRC符号生成装置の構成図である。
1・・・中央制御装置、 2・・・CRC符号生成装
置。
5・・・主記憶装置、 4・・・補助記憶装置、2
0・・・リード/ライト制御部。
21.22・・・アドレス演算部、
25・・・アドレスポインタ部、
24・、・CRC符号生成記憶部。
代理人弁理士 薄 1)利 幸1
才 1 図FIG. 1 is a block diagram of the system of the British predecessor of the present invention, and FIG. 2 is the same (a block diagram of a CRC code generation device. 1... Central control unit, 2... CRC code generation device. 5 ...Main storage device, 4...Auxiliary storage device, 2
0...Read/write control unit. 21.22...Address operation unit, 25...Address pointer unit, 24., CRC code generation storage unit. Representative patent attorney Susuki 1) Toshiyuki 1 year old 1 figure
Claims (1)
システムにおいて、あらかじめ主記憶装置に格納された
データに対し前記サイクリ破壊の可能性がある場合に、
再度、前述のデータに対し、サイクリック符号を生成し
、その結果と前もって記憶していた結果とを照合し、一
致した場合はデータ破壊がない、不一致の場合はデータ
破壊があると判定することを特徴とするメモリ破壊検証
方式。1. In a system having a main memory device and a cyclic code generation device, if there is a possibility of cyclic destruction of data stored in the main memory device in advance,
Generate a cyclic code again for the above-mentioned data, compare the result with the previously stored result, and determine that if they match, there is no data destruction, and if they do not match, it is determined that there is data destruction. A memory corruption verification method featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223743A JPS59116999A (en) | 1982-12-22 | 1982-12-22 | Memory destruction verifying system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223743A JPS59116999A (en) | 1982-12-22 | 1982-12-22 | Memory destruction verifying system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59116999A true JPS59116999A (en) | 1984-07-06 |
Family
ID=16802997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57223743A Pending JPS59116999A (en) | 1982-12-22 | 1982-12-22 | Memory destruction verifying system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59116999A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63129150A (en) * | 1986-05-08 | 1988-06-01 | Nippon Denso Co Ltd | Protecting method for study data in control device for internal combustion engine |
-
1982
- 1982-12-22 JP JP57223743A patent/JPS59116999A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63129150A (en) * | 1986-05-08 | 1988-06-01 | Nippon Denso Co Ltd | Protecting method for study data in control device for internal combustion engine |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS59116999A (en) | Memory destruction verifying system | |
JPS58125125A (en) | Starting method of program | |
JPH0317760A (en) | Data write confirming system | |
JPH0273420A (en) | Semiconductor disk device | |
JPS6341962A (en) | Program control device | |
JPH05342094A (en) | Computer device | |
JPH02227754A (en) | Disk cache control system | |
JPS60103446A (en) | Controller of auxiliary memory | |
JPH02103643A (en) | Interruption generation circuit for debug | |
JPH03292533A (en) | File correcting method | |
JPH01201728A (en) | Program correcting system | |
JPH0358217A (en) | Electronic disk subsystem | |
JPH0782447B2 (en) | DMA data transfer control device | |
Neumann | Disk-based program swapping in 8080-based microcomputers | |
JPS5972542A (en) | Correcting system of object program | |
JPH03260745A (en) | Duplex electronic disk device | |
JPS6128121B2 (en) | ||
JPS62162157A (en) | Program loading system | |
JPS63155346A (en) | Ram check system | |
JPH04105137A (en) | Check system for input/output function of computer | |
JPH01240941A (en) | Information processor | |
JPH06175940A (en) | Data processor | |
JPH0436424B2 (en) | ||
JPS5897194A (en) | Data processing method for bubble memory | |
JPH0480860A (en) | Program loading system |