JPS59116876A - マルチプロセツサシステムにおけるシグナルプロセツサ命令実行制御方式 - Google Patents

マルチプロセツサシステムにおけるシグナルプロセツサ命令実行制御方式

Info

Publication number
JPS59116876A
JPS59116876A JP57228856A JP22885682A JPS59116876A JP S59116876 A JPS59116876 A JP S59116876A JP 57228856 A JP57228856 A JP 57228856A JP 22885682 A JP22885682 A JP 22885682A JP S59116876 A JPS59116876 A JP S59116876A
Authority
JP
Japan
Prior art keywords
control
bit
busy
5igp
signal processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57228856A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6310464B2 (enrdf_load_stackoverflow
Inventor
Kazuhiro Hara
一広 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57228856A priority Critical patent/JPS59116876A/ja
Publication of JPS59116876A publication Critical patent/JPS59116876A/ja
Publication of JPS6310464B2 publication Critical patent/JPS6310464B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP57228856A 1982-12-23 1982-12-23 マルチプロセツサシステムにおけるシグナルプロセツサ命令実行制御方式 Granted JPS59116876A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57228856A JPS59116876A (ja) 1982-12-23 1982-12-23 マルチプロセツサシステムにおけるシグナルプロセツサ命令実行制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57228856A JPS59116876A (ja) 1982-12-23 1982-12-23 マルチプロセツサシステムにおけるシグナルプロセツサ命令実行制御方式

Publications (2)

Publication Number Publication Date
JPS59116876A true JPS59116876A (ja) 1984-07-05
JPS6310464B2 JPS6310464B2 (enrdf_load_stackoverflow) 1988-03-07

Family

ID=16882947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57228856A Granted JPS59116876A (ja) 1982-12-23 1982-12-23 マルチプロセツサシステムにおけるシグナルプロセツサ命令実行制御方式

Country Status (1)

Country Link
JP (1) JPS59116876A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS6310464B2 (enrdf_load_stackoverflow) 1988-03-07

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