JPS59115681A - Image pickup and recording device - Google Patents

Abstract

PURPOSE:To increase remarkably the number of pickup sheets even if a still picture is picked up, to save power and to increase the pickup time by supplying a power supply to a mechanism drive circuit and eliminating an unnecessary charge in synchronizing with a readout synchronizing signal generated thereafter. CONSTITUTION:A low potential barrier 40 (so-called anti-booming barrier) for excessive charge elimination is provided near a horizontal register, and further, an electron drain electrode 41 (so-called overflow drain) is provided adjacent to the barrier. When a high negative voltage is impressed to a horizontal register electrode 33 and an internal potential under the electrode is brought into a state shown in solid lines, the electric charge is transferred sequentially in high speed to a region II'' of the horizontal register part by impressing a pulse to a transfer electrode 32 of the image pickup section and the storage section. An excessive electric charge exceeding the potential barrier 40 among unnecessary charges injected to the region II'' over the potential barrier 40 formed lower than the potential level of regions III'', VI'' adjacent to the region II'' is eliminated in high speed into the electronic drain electrode 41.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an imaging and recording device that uses a solid-state imaging device to photograph moving images or still images and records them on a recording medium.

<Description of the Prior Art> In general, a video signal recording device has built-in recording means such as a head that rotates at high speed and a disk that rotates at high speed in order to enable recording of wideband signals.

When starting up these recording devices, it takes several seconds for the recording means to rotate at high speed and stably in synchronization with the synchronization signal.

Such a short start-up time becomes a particularly serious problem in devices that frequently start and stop recording means.

That is, the video signal input to the recording device during this period becomes unsuitable for reproduction and is wasted.

At the same time, the power consumed within the imaging device during this start-up period can also be said to be wasteful. For example, even if a scanning signal source for scanning an image pickup tube or image sensor does not perform scanning, it consumes a considerable amount of power just by producing periodic output, so this should never be ignored. Can not. This also applies to signal processing circuits in imaging and recording devices.

Therefore, when using a combination of an imaging device and a recording device outdoors (including cases where the imaging device and recording device are integrally formed), the recording device is stopped each time in order to reduce the power consumption of the recording device. Even if this is done, the ratio of the energization time to the effective signal period increases, so there is a drawback that it is not very effective in reducing power consumption.

Furthermore, if the imaging and recording device is specifically intended for capturing still images such as one field or one frame, the imaging and recording device can be turned on and off as needed. As a result, the problems mentioned above will be brought into closer focus.

Furthermore, when a solid-state image sensor is used as the image pickup means, it is necessary to remove unnecessary charges at the start of operation.

<Object of the Invention> It is an object of the present invention to provide an improved imaging and recording device capable of solving the problems of the prior art. Note that the imaging and recording device here refers to a device that is functionally integrated with a device that has an imaging function and a device that has a recording function, regardless of whether they are integrated or separate in appearance. do not have.

<Description of Embodiments> FIG. 1 is a schematic diagram of the vicinity of the boundary between the storage area and the horizontal shift register of a normal φ frame transfer type CCD.

Traditionally, single-phase drive has been used as the charge transfer method.

There are several methods such as 2-phase drive, 3-phase drive, and 4-phase drive methods, and the present invention can be applied to any of them, but for the sake of simplicity, the phasing drive method will be explained below as an example. .

The single-phase drive method referred to here is based on Japanese Patent Application Laid-open No. 55-1.
Publication No. 1394 ``Described in charge transfer device''-
The detailed operation is not necessary for the purpose of explanation, so it will be omitted.

In FIG. 1, 20 indicates a channel stop that prevents charge leakage between cells in the horizontal direction, and 24 indicates a polysilicon electrode in the storage area, and the area of this electrode 24 is a region of potential state in the silicon. Different areas I and areas ■
It consists of Reference numeral 25 denotes a region in silicon in which a virtual electrode is formed, and in the potential state in silicon, regions 1 to 2 constitute one cell. still,
Not only the storage section but also the imaging section is similarly composed of a plurality of light quantity cells, and is divided into a polysilicon electrode section and a virtual electrode section. 33 indicates a horizontal transfer register area. In this region, the polysilicon electrode is formed in a comb-tooth shape with diagonal lines, and below this polysilicon electrode are regions 1. It is divided into It. Here, region 1 has the same potential but is separated into two regions by a channel stop. The regions m and 'IV are each set to the same potential as the virtual electrode section 25 of the storage section.

FIG. 2 is a diagram showing the internal potential state of the COD having the configuration shown in FIG.

In FIG. 2, 32 is a polysilicon electrode of the storage section 24 of FIG. 1, and all the polysilicon electrodes of the storage section are connected in common, and a voltage for charge transfer is applied thereto. Below this polysilicon electrode 32 is region 1. as explained in FIG. It is divided into 1I, and region I has a higher potential state than region 2.

In the figure, the dotted line indicates a state in which the polysilicon electrode 32 has a high negative potential, and the solid line indicates the potential in a state in which the potential of the polysilicon electrode 32 is slightly negative or positive, respectively.

As shown in FIG. 2, the potential of the virtual electrode portion 25 in FIG. 1 is slightly higher in region (2) than in region (2). Also, the potential of this part is electrode 3
It does not depend on the voltage applied to 2 and is kept constant at the stem. Therefore, if a constant voltage is applied to the polysilicon electrode, charges will be accumulated, and if a pulsed voltage is applied, charges will be transferred, but further detailed explanation will be omitted. 3
3 indicates a polysilicon electrode of a horizontal transfer register. This electrode is separated from the other electrodes so that an independent voltage can be applied to it. The internal potential of this horizontal transfer register section is determined by the polysilicon electrode 3 shown in FIG.
It looks like the figure below 3.

FIG. 2, 20 shows the potential state of the channel stop section 0 The movement of charges in the horizontal transfer register section will be explained below. is transferred by applying a Norms voltage to the first
It enters the potential well region ■' in FIG. At this time, if a slightly negative or positive potential is applied to the polysilicon electrode 33 of the horizontal transfer register, the area 2 becomes the potential state shown by the solid line in FIG.
Enter the “region through ■”. Then, when a high negative potential is applied to this electrode 33, region I is formed.

■“The potential shifts to the state shown by the dotted line, and the area ■”
The charge present in the area is transferred to the area ■'' through the area ■''. At this time, if a slightly negative or positive potential is applied to the polysilicon electrode 33 of the storage section, this region
．． As shown by the solid line, the charge in the region (2) is transferred to the region (2). As a result, the charge transferred from the area ■ to the area ■'' of the storage section of the horizontal register as described above is transferred sequentially in the direction of the arrow in the horizontal register in the direction of ■-■→■→■. By applying a pulsed voltage to the polysilicon electrode 33 of the horizontal register, the charge transferred to the horizontal register can be transferred in the direction indicated by the arrow in Figure 1 and read out to the outside. The flow shows the same operation as the conventional frame-transfer type COD.

Here, consider the case at the start of operation, that is, when the power is turned on.

In order to quickly make the device ready for imaging after power is turned on, unnecessary charges such as dark current must be removed from the signal charge channel at high speed. In general CCD area sensors, excess charge can be removed by an excess charge removal mechanism (referred to as +jH normal anti-blooming structure) provided in the imaging section, etc., but unnecessary charges that are not excessive can be cleared at high speed. It was not possible to do so, and it was necessary to transfer the signal to the drain electrode of the output amplifier section in the same way as the signal load. It is also possible to have a structure in which a clear gate is provided adjacent to the charge channel of the storage section in the image sweeping section, but this will cause performance problems such as a reduction in the area of the light receiving section, a reduction in the transfer charge capacity, and a complicated pattern for IC fabrication. There were many problems with mass production.

Therefore, in this embodiment, as shown in FIG. 1, a low potential barrier 40 for removing excess charge is installed adjacent to the horizontal register.
(commonly known as an anti-blooming barrier) is provided, and an electron drain electrode 41 (commonly known as an overflow drain/) is provided adjacent to the barrier. Horizontal register electrode 33
By applying a high negative voltage to the transfer electrode 32 of the imaging section and storage section with the internal potential under the electrode as shown by the solid line, a pulse is applied to the transfer electrode 32 of the image pickup section and the storage section. are transferred in high-speed sequential order. Adjacent to region H, region 111. Among the unnecessary charges injected into the region ■'' through the potential barrier 40 which is made to have a lower potential level of IV, the lower barrier 40
Excess charge exceeding the t-drain electrode 41 is removed at high speed. Unnecessary charges remaining in the region 11 without being removed are transferred from the output amplifier to the horizontal register and removed at high speed.

Further, as shown in FIG. 2, the potential of the anti-blooming barrier 40 is made to fluctuate together with the potential of the area H by the horizontal transfer pulse, and is made higher than the potential level of the area (2). Therefore, during the signal transfer operation to the outside by the above-mentioned horizontal register δ register, the signal charges are prevented from flowing out beyond the barrier 40, and it becomes possible to always perform the accurate external transfer operation.

3 and 4 show the second embodiment, and FIGS. 5 and 6 show the third embodiment. The second embodiment is of a type in which an anti-pluming barrier 40 is provided adjacent to region (2). In this embodiment, during high-speed clearing, it is necessary to apply a transfer pulse to the horizontal register at the same frequency as the transfer pulse of the storage section. That is, as in the first embodiment described above, the imaging section and the storage section are driven to sequentially transfer the accumulated charges in the imaging section and the storage section to the region (2), and the electrode 3
By applying the above-mentioned drive signal to 3 and causing the potentials of regions I and 2 to alternately shift to the solid line and dotted line states, charges are sequentially injected into region 2 in the same manner as the operation of the horizontal register described above. The excess charge generated at this time flows out from the barrier 40 to the overflow drain 41, thereby clearing unnecessary charges accumulated in the imaging section and the storage section. In addition, in a normal horizontal transfer operation using a horizontal register, only the horizontal register part is driven without driving the storage part, so the charge input to area , and usually accurate signal transfer.

In the third embodiment, a clear gate 42 is provided in place of the anti-blooming clear, and the gate 42 is opened at the time of high-speed clearing, that is, the areas I and Il'l are moved from the position of the solid line to the position of the dotted line. In addition, a +1 distortion portion is provided as in the second embodiment.

By driving the storage section and part of the horizontal register at the same frequency, unnecessary charges in the imaging section and the storage section are cleared. That is, in the same manner as in the second embodiment described in 1-1, charges are sequentially injected from the storage section into the area H of the horizontal register, and charges sequentially injected into the area ■ are transferred to the area ■, and charges are sequentially injected into the area ■. The charge is caused to flow out through the gate with the potential shown by the dotted line, and the charge in the storage section is cleared.In addition, during the normal horizontal register transfer operation, the gate is closed, that is, region 1, ■ is shown by the solid line. The potential prevents signal charges from flowing out through the gate.

Hereinafter, an imaging apparatus using the solid-state imaging device shown in the above-mentioned embodiments 1 to 3 will be described.

FIG. 7 is a control block diagram of the imaging and recording device.

In the figure, 100 is an aperture and a shutter, and 1o1 is the aforementioned solid-state imaging device, and in this example, the CCD of the third embodiment having a clear gate is used.

102 is a video signal processing circuit, 1.03 is an NTSC adapter for obtaining an NTSC signal, and 104 is a magnetic disk 106.
105 is a recording head, 107 is a support disk for a magnetic disk 106, 1
08 is a rotating shaft, 110 is a CCI) drive circuit, 111 is a clock generator, 112 is a sequence control circuit that supplies timing signals to each circuit, 12o is a DC-DC converter that supplies power to each circuit, 121 is a batch' J-11
23 is a power switch.

Explain the operation. After passing through the aperture and shutter 00, the L;Z object light is projected onto the CCD 101 and converted into an electrical signal.

The signal processing circuit 102 converts this electrical signal into a constant video signal, determines the aperture value and shutter speed, and performs feedback control of the aperture and shutter 00. The video signal is output to the NTSC7 adapter 103, where it is converted into an NTSC signal, and the image of the subject can be monitored by connecting it to, for example, an electronic viewfinder.

The video signal is also output to the recording head 1.05 and recorded on the magnetic disk 106. CCDl01. .

Signal processing circuit 102. The NTSC7 adapter 103 motor drive circuit 104 etc. are controlled by control pulses from the clock generator 111, but the drive pulses of the CCD 101 have different voltage levels, the COD is a capacitive load, etc. ~110 is required. Further, when the switch 123 is inactive, the output of the battery 121 is stabilized by the DC-1)C:ff inverter 120 and power is supplied to these circuits and mechanisms.

From the clock generator 111, there is an imaging section transfer lock PI that transfers the 'N1 load of the imaging section of the CCD 101.

Accumulator transfer lock PS that transfers the charge in the accumulator of CCD 101, horizontal transfer lock S that drives the horizontal transfer unit of C0DIOI, and signal CG that opens and closes the clear gate.
is output to the COD drive circuit 110, and the vertical synchronization signal of the television is output to the signal processing circuit 102. Drive circuit 10
Output to 4th grade. The voltage level of the COD control signal is converted by the CCD drive circuit 110 and is indicated by adding "l".

The operation of these clocks and the operation of each circuit will be explained using the timing chart of FIG. 9. First, the operation when the power is turned on will be explained.

As shown in FIG. 7, the sequence control circuit 112 is provided with a standby mode terminal ″+ (hereinafter referred to as SBM terminal) T.
A power-up clear capacitor C is connected between the SBM terminal T and the ground, and the capacitor C is connected to the output of the DC-DC converter via a time constant control resistor R.

When the power switch 123 is pressed, each power supply voltage output (FIG. 9(A)) of the DC-DC converter 120 is NTSC.
Adapter 103. It is supplied to each circuit such as the motor/drive circuit 104 and the sequence control circuit 112, and to the capacitor C. When the sequence control circuit 112 is supplied with the power supply voltage, it resets the internal program to its initial state using a reset pulse and enters a processing routine. First, the internal terminal voltage in standby mode (Fig. 9 (Di)) is set to H level to prevent the generation of each clock for driving the CCD. This period T1 is called the standby period. Synchronization signal VH (Figure 9 (g)
) is sent to the drive circuit 104 and used for motor phase control. During this T1 period, the capacitor C is gradually charged, and when the SBM terminal T reaches a certain set voltage, the voltage at the SBM internal terminal changes from the H level to the L level. Vertical transfer pulse pI is synchronized with the fall of vertical synchronization signal ■ which occurs next to the fall from H level to L level.
: ps: and the seniority %li caused by the dark current existing in the storage section is removed through the overflow drain (T2, T3 period). During this unnecessary charge removal period, the vertical transfer operation is performed at least multiple times so that unnecessary charges are completely removed without any spillage. In this embodiment, two vertical transfer operations are illustrated.

When the vertical transfer operation ends, information charges corresponding to the subject image are accumulated in the imaging section during the T3 period. During this time, the clear gate pulse CG is at H level and the horizontal transfer pulse S' is also output, so that unnecessary charges in the horizontal transfer register are completely removed. .

Then, in the next T4 period, "vertical transfer pulses PI' and PS' are sent out in synchronization with the vertical synchronization signal VH as a read synchronization signal for reading from the image sensor, and the information charges in the image sensor are transferred to the storage section.

Furthermore, during the T5 period, an electrical signal corresponding to the information charge is read out from the horizontal transfer register, and control values for controlling the aperture and shutter are calculated based on this electrical signal. By the way, T
If the aperture and shutter control values are calculated by a photometric element other than the image sensor in the I or T2 period, and the accumulation operation is performed at the aperture value and shutter speed according to the amount control values in the accumulation period T3. , the electrical signal output during the T5 period passes through the video signal processing circuit 102 and is then sent to the recording head 105.
is recorded on the disk 106 by the following.

In addition, during the standby mode period T2, the motor/drive circuit 1
It is determined according to the time required for the disk 106 to rotate at a speed synchronized with the television vertical synchronization signal VH after power is supplied to the television VH.

Although the operation of this embodiment has been explained based on the third embodiment having a clear gate, the operation of the first embodiment has been explained based on the third embodiment having a clear gate. As described above, in the second embodiment as well, the clearing operation can be performed by sending out the vertical and horizontal transfer locks.

In this embodiment, the standby time is configured by a timer means using a capacitor, but it may also be determined by a phase lock signal of the disk or drive motor.

<Description of Effects> By supplying power to the mechanism drive circuit that drives the recording mechanism as in the present invention and removing unnecessary charges in synchronization with the readout synchronization signal that is generated thereafter, power can be saved and the shooting time can be reduced. In addition, when shooting still images, the number of shots taken has increased significantly.

Furthermore, when unnecessary charges are removed, it becomes possible to use the necessary vertical and horizontal transfer pulses for normal readout operations, and the image sensor driving circuit is greatly simplified.

That is, when removing unnecessary charges, it is sufficient to simply increase the number of vertical and horizontal transfer pulses.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an example of an image sensor that can be used in the present invention, FIG. 2 is a schematic diagram showing the potential inside the image sensor shown in FIG. 1, and FIG. FIG. 4 is a schematic diagram showing the potential inside the image sensor of FIG. 3; FIG. 5 is a configuration diagram showing still another embodiment of the image sensor that can be used in the present invention. , Figure 6 is the fifth
7 is a control block diagram of the imaging device, FIG. 8 is a block diagram of CCD drive pulse generation, and FIG. 9 is a timing chart of CCD drive pulses. 20 is a channel stop, 32 is a vertical transfer electrode, 33 is a horizontal transfer electrode, 40 is a low potential barrier, 41 is a drain electrode, 42 is a gate electrode for charge removal, 101. id: CCD. 102 is a video signal processing circuit, 110 is a CCD drive circuit, 11 to 1 are clock generators, 104 is a disk recording device, and 123 is a power switch. Applicant Canon Co., Ltd. Agent Gi Marushima −

Claims (1)

[Claims] (1) a solid-state image sensor that captures a subject image; an image sensor drive circuit that generates a drive clock that drives the image sensor;
A mechanism drive circuit that drives a recording mechanism for recording an image signal obtained from the image sensor, a signal generation circuit that generates a read synchronization signal for reading the image signal from the image sensor, a power switch, and the power switch. control means for supplying power to the mechanism drive circuit when the synchronous signal is turned on, and then controlling the element drive circuit to remove unnecessary charges accumulated in the element in synchronization with the generation of the synchronization signal. An imaging and recording device characterized by: