JPS5911566U - Pedestal level detection circuit - Google Patents

Pedestal level detection circuit

Info

Publication number
JPS5911566U
JPS5911566U JP10594982U JP10594982U JPS5911566U JP S5911566 U JPS5911566 U JP S5911566U JP 10594982 U JP10594982 U JP 10594982U JP 10594982 U JP10594982 U JP 10594982U JP S5911566 U JPS5911566 U JP S5911566U
Authority
JP
Japan
Prior art keywords
signal
level
detection circuit
width
pedestal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10594982U
Other languages
Japanese (ja)
Other versions
JPH0411411Y2 (en
Inventor
三野　芳勝
Original Assignee
リ−ダ−電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by リ−ダ−電子株式会社 filed Critical リ−ダ−電子株式会社
Priority to JP10594982U priority Critical patent/JPS5911566U/en
Publication of JPS5911566U publication Critical patent/JPS5911566U/en
Application granted granted Critical
Publication of JPH0411411Y2 publication Critical patent/JPH0411411Y2/ja
Granted legal-status Critical Current

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  • Picture Signal Circuits (AREA)
  • Television Receiver Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本考案の一実施例であるペデスタル・レベル
検出回路を示す。第２図は、第１図の回路内の信号波形
を示す。 〔符号説明〕、２：オペアンプ、４．６＝抵抗器、８．
１２：コンデンサ１．１０：ダイオード、１４：出力端
子。FIG. 1 shows a pedestal level detection circuit which is an embodiment of the present invention. FIG. 2 shows signal waveforms within the circuit of FIG. [Explanation of symbols], 2: operational amplifier, 4.6 = resistor, 8.
12: Capacitor 1.10: Diode, 14: Output terminal.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）ビデオ信号のペデスタル・レベルを検出スるため
の回路において、 （イ）ペデスタル・レベルを与えるため信号を蓄積する
ための蓄積装置１２と、 （ロ）　該−積装置の前記信号のレベルを上昇させる上
昇装置＋Ｖ、４．１２と、 （ハ）前記蓄積装置の前記信号のレベルがビデオ信号の
ペデスタル・レベルよりも大きくなるときを検出するた
めの検出装置２．　６．　８であって、該検出装置は少
なくとも前記ビデオ信号の同期信号の幅よりも大きな幅
の信号に応答すること、及び に）前記検出装置に応答して前記蓄積装置の信号のレベ
ルを前記ペデスタル−レベルへ減少すせる減少装置１０
と、 から成るペデスタル中レベル検出回路。(1) A circuit for detecting a pedestal level of a video signal, comprising: (a) a storage device 12 for storing a signal to provide a pedestal level; and (b) a level of the signal of the product device. (c) a detection device for detecting when the level of the signal of the storage device becomes greater than the pedestal level of the video signal; 2. 6. 8) the detection device is responsive to a signal having a width at least greater than the width of a synchronization signal of the video signal; Reduction device 10 for reducing to level
A pedestal medium level detection circuit consisting of and. （２）実用新案登録請求の範囲第１項記載の回路におい
て、該検出回路が積分器を含む負のピーク検出回路であ
り、前記積分器が少なくとも前記ビデオ信号の同期信号
の幅よりも広い幅の信号を通すような積分定数を有する
こと、を特徴とする回路。(2) Utility model registration The circuit according to claim 1, wherein the detection circuit is a negative peak detection circuit including an integrator, and the integrator has a width at least wider than the width of the synchronization signal of the video signal. A circuit characterized in that it has an integral constant that allows a signal to pass through.
JP10594982U 1982-07-13 1982-07-13 Pedestal level detection circuit Granted JPS5911566U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10594982U JPS5911566U (en) 1982-07-13 1982-07-13 Pedestal level detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10594982U JPS5911566U (en) 1982-07-13 1982-07-13 Pedestal level detection circuit

Publications (2)

Publication Number Publication Date
JPS5911566U true JPS5911566U (en) 1984-01-24
JPH0411411Y2 JPH0411411Y2 (en) 1992-03-23

Family

ID=30248137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10594982U Granted JPS5911566U (en) 1982-07-13 1982-07-13 Pedestal level detection circuit

Country Status (1)

Country Link
JP (1) JPS5911566U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53140342U (en) * 1977-04-13 1978-11-06
JPS54103140U (en) * 1977-12-28 1979-07-20

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53140342U (en) * 1977-04-13 1978-11-06
JPS54103140U (en) * 1977-12-28 1979-07-20

Also Published As

Publication number Publication date
JPH0411411Y2 (en) 1992-03-23

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