JPS58166186U - Dropout compensation circuit - Google Patents

Dropout compensation circuit

Info

Publication number
JPS58166186U
JPS58166186U JP6318482U JP6318482U JPS58166186U JP S58166186 U JPS58166186 U JP S58166186U JP 6318482 U JP6318482 U JP 6318482U JP 6318482 U JP6318482 U JP 6318482U JP S58166186 U JPS58166186 U JP S58166186U
Authority
JP
Japan
Prior art keywords
circuit
compensation circuit
signal
dropout compensation
dropout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6318482U
Other languages
Japanese (ja)
Inventor
西林 厚
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP6318482U priority Critical patent/JPS58166186U/en
Publication of JPS58166186U publication Critical patent/JPS58166186U/en
Pending legal-status Critical Current

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  • Television Signal Processing For Recording (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のドロップアウト補償回路の構成図、第2
図は従来の回路の信号図、第3図は本考案のドロップア
ウト補償回路の構成図、第4図は本考案の回路の信号図
である。 図において、1はFM増巾回路、2.7はゲート回路、
3はリミッタ−14はドロップアウト検出回路、5はゲ
ートパルス成形回路、6はIH遅延回路、8は混合回路
、9は検出レベル調整器、10は電圧発生器である。図
中、同一符号は同一または相当部分を示す。
Figure 1 is a configuration diagram of a conventional dropout compensation circuit;
FIG. 3 is a signal diagram of a conventional circuit, FIG. 3 is a block diagram of a dropout compensation circuit according to the present invention, and FIG. 4 is a signal diagram of a circuit according to the present invention. In the figure, 1 is an FM amplification circuit, 2.7 is a gate circuit,
3 is a limiter, 14 is a dropout detection circuit, 5 is a gate pulse shaping circuit, 6 is an IH delay circuit, 8 is a mixing circuit, 9 is a detection level adjuster, and 10 is a voltage generator. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] FM信号処理に於てFM信号レベル欠落を検出する回路
、FMIH遅延回路、ゲート回路、混合回路を有するド
ロップアウト検出回路に於て該FMレベル検出回路の検
出レベルを特殊再生信号又はFF信号にて切替可能にし
たドロップアウト補償回路。
In FM signal processing, in a dropout detection circuit having a circuit for detecting FM signal level loss, an FMIH delay circuit, a gate circuit, and a mixing circuit, the detection level of the FM level detection circuit is detected by a special reproduction signal or an FF signal. Switchable dropout compensation circuit.
JP6318482U 1982-04-29 1982-04-29 Dropout compensation circuit Pending JPS58166186U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6318482U JPS58166186U (en) 1982-04-29 1982-04-29 Dropout compensation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6318482U JPS58166186U (en) 1982-04-29 1982-04-29 Dropout compensation circuit

Publications (1)

Publication Number Publication Date
JPS58166186U true JPS58166186U (en) 1983-11-05

Family

ID=30073292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6318482U Pending JPS58166186U (en) 1982-04-29 1982-04-29 Dropout compensation circuit

Country Status (1)

Country Link
JP (1) JPS58166186U (en)

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