JPS59115646A - Continuous call type storage exchange - Google Patents
Continuous call type storage exchangeInfo
- Publication number
- JPS59115646A JPS59115646A JP57223745A JP22374582A JPS59115646A JP S59115646 A JPS59115646 A JP S59115646A JP 57223745 A JP57223745 A JP 57223745A JP 22374582 A JP22374582 A JP 22374582A JP S59115646 A JPS59115646 A JP S59115646A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- control information
- call
- call control
- accessed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
Abstract
Description
【発明の詳細な説明】
発明の利用分野
本発明は、2重化された蓄積交換機の系切替時、確立し
ている呼の連続性保証に関するもの理装置や記憶装置は
個別に2重化され、呼の生起や確立に伴う記憶装置の書
替は動作系のみ行われていた。この結果、何らかの原因
で系が切替わると呼の状態が格納されていない待期中の
記憶装置を用いて系の制御を行うため、通信中の呼は初
期設定され、新たに呼の確立手順からおいて、両系の処
理を同期1−で動作させる事なくして、系の切替を行う
場合、通信中の呼の装置を、プログラム及びワークエリ
ア用メモリと呼制御情報や通信データを格納するデータ
用メモリに分割し、2重化したデータ用メモリに動作中
の系よシ同時にアクセスし同一の状態にしておき、系切
替時一方のデータ用メモリを他方する。第1図において
、+Vi処理装置N <CPUo/1゜最後のo/+
842重化系の区別を示す。以下全て同様)、2はプロ
グラム及びワークエリア用メモリpMo/1.5け内部
バスBUSO/+ 、 4けメモリ選択回路MSEL、
5けデータ用メモリ(DI)、6は回線制御部(LCT
LO/1)、7は回線選択回路(LSEL)。DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to guaranteeing the continuity of an established call when switching over a duplexed storage/switching system. However, when a call is generated or established, the storage device is rewritten only in the operating system. As a result, if the system is switched for some reason, the system is controlled using the standby storage device that does not store the call status, so the current call is initialized and a new call establishment procedure is started. When switching between systems without operating the processes of both systems in synchronization, the call equipment during communication is transferred to memory for programs and work areas, and data for storing call control information and communication data. The dual data memory is accessed simultaneously by both operating systems to maintain the same state, and when the system is switched, one data memory is transferred to the other. In FIG. 1, +Vi processing device N <CPUo/1° last o/+
The distinction between 842 and multiplex systems is shown. 2 is a program and work area memory pMo/1.5 digits internal bus BUSO/+, 4 digits memory selection circuit MSEL,
5 data memory (DI), 6 line control unit (LCT)
LO/1), 7 is a line selection circuit (LSEL).
8は多重化部(MpX)、9は回線対応部(w)である
。本装置において、CpUは一般的な処理装置であシ、
マイクロコンビーータ等で構成できるものである。PM
は本装置を制御するプログラムヤ、プログラムで使用す
るワークエリア用のメモリであシRAMで構成される。8 is a multiplexing section (MpX), and 9 is a line correspondence section (w). In this device, the CPU is a general processing device;
It can be configured with a micro combinator or the like. PM
It consists of a program controller that controls this device, and a RAM that serves as a work area memory used by the program.
BUSは、CPU。BUS is CPU.
PM、DM、 LCTL を結合する本装置の内部バス
である。DMは1本装置が蓄積交換を行うデータや。This is an internal bus of this device that connects PM, DM, and LCTL. DM is data that is stored and exchanged by a single device.
ユーザの呼制御情報を格納するためのRAMである。L
CTLは不装置で交・換するゲータをLUと消の間で授
受するためのダイレフ!・メモリアクセスコントローラ
である。LSEIJd 2重化系の切替を行うための選
択回路である。LMpXは、回線毎にあるシリアル/バ
ラワレ変換機能を持つ多数のLUを多重化するための多
重化回路である。MSELとDhfを一督する事が本装
置の特徴でちり、 MSELはDI#J/Iを動作中の
系に接続するよう動作する。This is a RAM for storing user call control information. L
CTL is a die reflex for sending and receiving gators that are exchanged without equipment between LU and UE! - It is a memory access controller. LSEIJd This is a selection circuit for switching the duplex system. LMpX is a multiplexing circuit for multiplexing a large number of LUs each having a serial/separate conversion function for each line. A feature of this device is that it controls MSEL and Dhf, and MSEL operates to connect DI#J/I to the operating system.
この事により、動作中の糸のCpU又はLCTLよシD
Mo7+−\同時にアクセスする事ができ同一の内容を
薔き込む事が可能になる。尚DMの読み出し時はCPU
oの系からはDMoをCPU1の系からはDMl・をア
クセスする。この結果、動作系をCPU0からCPU1
へ切替えた場合、CPU1は呼制御情報及び蓄積データ
情報を全て引継ぐ事になp、pM1内のプログラム制御
の下に確立中の呼は連続したままサービスを再開できる
。This allows the CpU or LCTL of the thread to be
Mo7+-\ can be accessed at the same time and the same content can be inserted. Furthermore, when reading DM, the CPU
The o system accesses DMo, and the CPU 1 system accesses DMl. As a result, the operating system is changed from CPU0 to CPU1.
When switching to pM1, the CPU 1 takes over all the call control information and accumulated data information, and the service can be resumed while the call being established under program control in pM1 continues.
次に第2図を用いて、MSELの動作を詳しく説明する
。第2図において、10は2−1選択回路(2−ISE
L) 、 11けゲート回路である。2−1SELはB
USよpDMへ送る信号(アドレス、書込みデータ、制
御信号)を選択する機能を有する。ゲート回路は、DM
からBUSへの信号を制御するものであシ、アクセス系
からのストローブ信号によりDM系を切替る時、切替前
の呼制御データ及び蓄−データを引継ぐことができるの
で1通信中の呼を切断する事なく通信を再開するのに効
果が凌る。Next, the operation of the MSEL will be explained in detail using FIG. In FIG. 2, 10 is a 2-1 selection circuit (2-ISE
L) is an 11-gate circuit. 2-1SEL is B
It has the function of selecting signals (address, write data, control signals) to be sent from US to pDM. The gate circuit is DM
When switching the DM system using a strobe signal from the access system, the call control data and stored data before switching can be inherited, so one call in progress can be disconnected. It is very effective in resuming communication without having to do anything.
第1図は本発明の一実施例の蓄積交換機のブロック図、
第2図は第1図のMSELの回路図である。
1:処理装置、
2ニブログラム及びワークエリア用メモリ。
5:内部バス、 4:メモリ選択回路、5:デー
タ用メモリ、6:回線制御部、7:回線選択回路、
8:多重化部、9二回線対応部、 40 : 2−1
選択回路、11:ゲート回路。
代理人弁理士 薄 1)利 幸
才 1 図
5
牙 2 図FIG. 1 is a block diagram of a storage and forwarding machine according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of the MSEL of FIG. 1. 1: Processing unit, 2 Niprogram and work area memory. 5: Internal bus, 4: Memory selection circuit, 5: Data memory, 6: Line control section, 7: Line selection circuit,
8: Multiplexing section, 9 two-line corresponding section, 40: 2-1
Selection circuit, 11: Gate circuit. Representative Patent Attorney Susuki 1) Kosai Toshi 1 Figure 5 Fang 2 Figure
Claims (1)
て、記憶装置をプログラム及びワークエリア用メモリと
交換データ蓄積と呼制御情報格納用メモリに分割し、動
作中の系より2重化された両方の交換データ蓄積と呼制
御情報格納用メモリに同時に書き込む機能を設けた事を
特徴とする呼連続形蓄積交換機。1. In a storage/switching system that uses a standby standby system with a duplex configuration, the storage device is divided into memory for programs and work areas, memory for exchange data storage, and memory for storing call control information, and the system is duplicated from the operating system. 1. A continuous call storage switching system characterized by having a function of storing both exchange data and writing to a memory for storing call control information at the same time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223745A JPS59115646A (en) | 1982-12-22 | 1982-12-22 | Continuous call type storage exchange |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223745A JPS59115646A (en) | 1982-12-22 | 1982-12-22 | Continuous call type storage exchange |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59115646A true JPS59115646A (en) | 1984-07-04 |
Family
ID=16803031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57223745A Pending JPS59115646A (en) | 1982-12-22 | 1982-12-22 | Continuous call type storage exchange |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59115646A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011175382A (en) * | 2010-02-23 | 2011-09-08 | Nippon Telegr & Teleph Corp <Ntt> | Cluster system, and system switching method in cluster system |
-
1982
- 1982-12-22 JP JP57223745A patent/JPS59115646A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011175382A (en) * | 2010-02-23 | 2011-09-08 | Nippon Telegr & Teleph Corp <Ntt> | Cluster system, and system switching method in cluster system |
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