JPS59115623A - Pll - Google Patents

Pll

Info

Publication number
JPS59115623A
JPS59115623A JP57232350A JP23235082A JPS59115623A JP S59115623 A JPS59115623 A JP S59115623A JP 57232350 A JP57232350 A JP 57232350A JP 23235082 A JP23235082 A JP 23235082A JP S59115623 A JPS59115623 A JP S59115623A
Authority
JP
Japan
Prior art keywords
dynamic range
pll
amplitude limiter
voltage
vcc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57232350A
Other languages
Japanese (ja)
Inventor
Hiroaki Ikejiri
池尻　博明
Hiroyuki Chihara
博幸 千原
Masuo Tsuji
辻　満寿夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57232350A priority Critical patent/JPS59115623A/en
Publication of JPS59115623A publication Critical patent/JPS59115623A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain an optimum dynamic range without changing the characteristic of a PLL within the dynamic range by constituting the PLL of a phase comparator, a low-pass filter, a voltage controlled oscillator and an amplitude limiter and limiting an output voltage range of the low-pass filter by the amplitude limiter. CONSTITUTION:In the figure, 1 is an external input signal, 2 is the phase comparator PD, 3 is the LPF, 4 is the VCO, 5 is the amplitude limiter, 6, 7 are Zener diodes, 8 is a power supply voltage Vcc terminal, and 9 is a power supply voltage VG terminal. But the relation of Vcc>VG is selected. In selecting a Zener voltage VZ1 of the Zener diodes 6, 7 as 2Vz1>Vcc-VG, an output voltage range VLPF of the LPF3 becomes VLPF=2Vz1-(Vcc-VG). Then, in changing the Zener voltage Vz1 in response to the applications of the PLL, the dynamic range to each application is made optimum. In this case, since it is not required to give any alteration to the PD2, LPF3 and VCO4, the dynamic range is made optimum without changing the locking characteristic, steady-state characteristic and transient response characteristic in the optimized dynamic range by the amplitude limiter 5.

Description

【発明の詳細な説明】 本発明にＰＩＪＬに関する。[Detailed description of the invention] The present invention relates to PIJL.

一般的には、ｐＨ，Ｌとは、電圧制御発掘器（以下、Ｖ
ＣＯといり）の出力信号の位相と、外部入力信号の位相
とを位相比較ａ（以下、ＦＤという）にて比較し、２信
号の位相差に応じて出力されるＰ　］）出力を低減フィ
ルタ（以下、ＬＰＦと一′））に入力し、このＬＰ’Ｆ
出力をもってｖｅＤｔ振周波数周波数するよう動作する
回路でるシ、汎用のＰＬＬ−ＩＣで１ｄｓＰＬＬのダイ
ナミックレンジ全仏くとっている。In general, pH and L are voltage-controlled excavators (hereinafter referred to as V
The phase of the output signal of the CO and the external input signal is compared with the phase of the external input signal using a phase comparison a (hereinafter referred to as FD), and the output is reduced according to the phase difference between the two signals. (hereinafter referred to as LPF), and input this LP'F
A circuit that operates so that the output has the veDt oscillation frequency is a general-purpose PLL-IC that has the full dynamic range of a 1ds PLL.

ところが、このダイナミックレンジの広い汎用ＰＬＬ−
ＩＣ’ｉ使用する場合、その用途によっては、不要なダ
イナミックレンジが生じるため、外部入力信号が脱落し
たり、ｔりるいは外部入力信号に雑音が混入すると、Ｐ
ＬＬが不要なダイナミックレンジ１で応答してし１うと
同時に、次に正常な外部入力信号を入力しても、ＶＣＯ
発振周波数が所殻の発振周波数に復帰するのに時間がか
かつてし１うという欠点がめった。However, this general-purpose PLL with a wide dynamic range
When using an IC'i, an unnecessary dynamic range may occur depending on the application, so if the external input signal is dropped or noise is mixed into the external input signal, the P
Even if LL responds with an unnecessary dynamic range of 1 and a normal external input signal is input, the VCO
A drawback is that it often takes a long time for the oscillation frequency to return to the original oscillation frequency.

本発明はかかる欠点を除去したもので、その目的は、ダ
イナミックレンジを広くとっている汎用ＰＬＬ−工０全
使用する場合、ダイナミックレンジ内でのＰＬＬの同期
特性、定常特性、過渡応答特性を変えることなく、その
用途に応じて、ダイナミックレンジを自由に調整し、最
適なダイナミックレンジを得ることのできる回路を提供
するものでるる。The present invention eliminates such drawbacks, and its purpose is to change the synchronization characteristics, steady state characteristics, and transient response characteristics of the PLL within the dynamic range when using a general-purpose PLL with a wide dynamic range. The present invention provides a circuit that can freely adjust the dynamic range and obtain the optimum dynamic range according to the application.

以下、実施例に基づいて不発明の詳細な説明する。Hereinafter, the invention will be described in detail based on examples.

第１図は、一般的なＰＬＬのブロック図で１．１は外部
入力信号端子、２はＦＤ、３はＬＦＦ。FIG. 1 is a block diagram of a general PLL, where 1.1 is an external input signal terminal, 2 is an FD, and 3 is an LFF.

４（ケＶＯＤである。この動作は前述の通シでるる。4 (VOD). This operation is the same as described above.

第１図にかいで、ＦＤ及びＶＯＤが汎用ＰＬＬ−ＩＣで
構成されている場合、そのダイナミックしくジを変更す
ることはできない。また、不要なダイナミックレンジに
葦でＰＬＬが応答すること、及び、その後正常な外部入
力したときの応答速度が遅いことという欠点のみに注目
すれば、ＬＰＦ時定数を変更することや考えられるが、
ＬＰＦ時定数全変更すると、ＰＬＬの同期特性、定常特
性。As shown in FIG. 1, if the FD and VOD are constructed of general-purpose PLL-ICs, their dimensions cannot be dynamically changed. Also, if we focus only on the shortcomings of the PLL responding to an unnecessary dynamic range and the slow response speed when receiving normal external input, it is possible to change the LPF time constant.
When the LPF time constant is completely changed, the synchronization characteristics and steady-state characteristics of the PLL change.

過渡応答特性が影響を受けでし１うため、ＬＰＦ時定数
ヲ変更して前記の欠点を改善することはできない。Since the transient response characteristics are not affected, the above drawback cannot be improved by changing the LPF time constant.

第２図は、本発明のＰＬＬのブロック図で＝ｌ、１は外
部人力信号端子、２はＦＤ、　３はＬＰＦ。FIG. 2 is a block diagram of the PLL of the present invention, where 1 is an external human input signal terminal, 2 is an FD, and 3 is an LPF.

４はＶＯＤ、５は振幅制限器である。振幅制限器５は、
Ｉ、Ｐ’Ｆ３の出力電圧範囲全制限しており、ＶＯＯ４
の発振周波数はＩ、ＰＩＦ３の出力電圧に制御される。4 is a VOD, and 5 is an amplitude limiter. The amplitude limiter 5 is
I, P'F3 output voltage range is completely limited, VOO4
The oscillation frequency of I is controlled by the output voltage of PIF3.

従って、Ｖ　ａ○４の見損周波数範囲は振幅制限器５に
よシ変更することが可能となシ、ＰＬＬのダイナミック
レンジの変更が容易に行なえることがわかる。この振幅
制限器５による振幅制限値は任意に設定することができ
るため、ダイナミックレンジは任意に変更することがで
きる。Therefore, it can be seen that the missed frequency range of Va○4 can be changed by the amplitude limiter 5, and the dynamic range of the PLL can be easily changed. Since the amplitude limit value by the amplitude limiter 5 can be set arbitrarily, the dynamic range can be changed arbitrarily.

また、このｐＬｆｆでは、ＦＤ２　、　ＬＰＦ’３　、
ＶＯＯ４を何ら変更する必要もないため、振幅制限器５
によって最適化したダイナミックレンジ内での同期特性
、定常特性、過渡応答特性と、振幅制限器５のない場合
の広いダイナミックレンジ内での各特性とは、全く同一
のものとすることができる。Also, in this pLff, FD2, LPF'3,
Since there is no need to change VOO4, the amplitude limiter 5
The synchronization characteristics, steady-state characteristics, and transient response characteristics within the dynamic range optimized by the above and the characteristics within a wide dynamic range without the amplitude limiter 5 can be made completely the same.

第６図は、本発明の一実施例であシ、１は外部。FIG. 6 shows an embodiment of the present invention, where 1 indicates the outside.

入力信号、２はＦＤ、５はＬＰＦ、４はＶＯＯ１５は振
幅制限器、６．７はツェナーダイオード、８は電源電圧
Ｖａｏ端子、９は電源電圧ＶＧ端子である。ただし、Ｖ
ＯＯ＞ＶＧである。第３図においては、振幅制限器５を
ツェナーダイオード６．７で構成した例を示している。Input signals include 2, FD, 5, LPF, 4, VOO, 15, amplitude limiter, 6.7, Zener diode, 8, power supply voltage Vao terminal, and 9, power supply voltage VG terminal. However, V
OO>VG. FIG. 3 shows an example in which the amplitude limiter 5 is composed of Zener diodes 6.7.

ツェナーダイオード６゜７のツェナー電圧ＶＺＩ全 ２Ｖｚｌ　〉ｖａ　ｃ−Ｖ。Zener diode 6°7 Zener voltage VZI total 2Vzl〉va　c-V.

と選ぶと、ＬＦＦ５の出力電圧範囲ＶＬＰＦはＶＬＰＦ
＝２　Ｖ　Ｚ　ｌ　−（、Ｖ　ＯＯ−４Ｇ　）と表わす
ことができる。従って、ツェナー電圧ＶＺＩ’ｉ、ＰＬ
Ｌの用途に応じて変更すれば、各用途に対するダイナミ
ックレンジを最適なものとすることができる。萱ｆｃ、
この場合も第２図の場合と同様、ＰＬＬの同期特性、定
常時性９過渡応答特性を変えることなく、ダイナミック
レンジを最適なものとすることができる。If you choose , the output voltage range VLPF of LFF5 is VLPF
It can be expressed as =2VZl-(,VOO-4G). Therefore, the Zener voltage VZI'i, PL
By changing L depending on the usage, the dynamic range for each usage can be optimized.萱FC,
In this case, as in the case of FIG. 2, the dynamic range can be optimized without changing the synchronization characteristics and steady-state transient response characteristics of the PLL.

尚、第２図、第６図は、本発明の災施例であ）、例えば
ＶＯＯ４の出力信号を分周する分周器がＰＬＬの構成要
素となっていても、本発明は応用可能である。Note that FIGS. 2 and 6 are practical examples of the present invention); for example, even if a frequency divider that divides the output signal of VOO4 is a component of a PLL, the present invention is applicable. be.

以上の例にみられるように、’　Ｌ　Ｐ　Ｆの出力電圧
範囲を振幅制限器によって制限し、その制限され７ＣＬ
ＰＦ出力電圧をもって■ＣＤ発振周波数全制御すること
によシ、一般的にはダイナミックレンジを広くしている
汎用ＰＬＬ−工Ｃを使用する場合でも、その用途に応じ
て、最適なダイナミックレンジを設定することができる
。従って、不要なダイナミックレンジ１でＰＬＬが応答
すること、めるいは、不要なロックレンジ１でＰＬＬが
応答した後、正常な外部入力信号全人力しても、ＶＣＯ
発振周波数が所要の発振周波数に復帰する１で時間がか
かることという従来の欠点を解消している。As seen in the above example, the output voltage range of 'L P F is limited by an amplitude limiter, and the limited 7CL
By fully controlling the CD oscillation frequency using the PF output voltage, the optimal dynamic range can be set according to the application, even when using a general-purpose PLL-C, which generally has a wide dynamic range. can do. Therefore, if the PLL responds with an unnecessary dynamic range of 1, or in other words, after the PLL responds with an unnecessary lock range of 1, even if all the normal external input signals are applied, the VCO
This eliminates the conventional drawback that it takes time for the oscillation frequency to return to the required oscillation frequency.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は一般的なＰＬＬのブロック図、第２図は本発明
のＰＬＬのブロック図、第３図は不発明の一実施例であ
る。 １・・・外部人カイｇ号　　　２・・・位相比較器３・
・・低減フィルター　　４・・・電圧制御発奈器５・・
・振幅制限器 ６．７・・・ツェナーダイオード ８・・・電源電圧Ｖａａ端子　９・・・電源電圧ＶＧ端
子以　　　上FIG. 1 is a block diagram of a general PLL, FIG. 2 is a block diagram of a PLL according to the invention, and FIG. 3 is an embodiment of the invention. 1...External Kai-g 2...Phase comparator 3.
...Reduction filter 4...Voltage control generator 5...
・Amplitude limiter 6.7...Zener diode 8...Power supply voltage Vaa terminal 9...Power supply voltage VG terminal or higher

Claims (1)

【特許請求の範囲】 、位相比較器、低減フィルター、電圧制御発振器。 振幅制限器よυ構成され、前記低減フィルタの出力電圧
範ｆＩ！Ａ全前記振幅制限器によって制限すること全特
徴とするＰＬＬ０[Claims] , phase comparator, reduction filter, voltage controlled oscillator. The amplitude limiter is configured to have an output voltage range fI! of the reduction filter. A PLL0 characterized in that it is limited by the amplitude limiter.
JP57232350A 1982-12-22 1982-12-22 Pll Pending JPS59115623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57232350A JPS59115623A (en) 1982-12-22 1982-12-22 Pll

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57232350A JPS59115623A (en) 1982-12-22 1982-12-22 Pll

Publications (1)

Publication Number Publication Date
JPS59115623A true JPS59115623A (en) 1984-07-04

Family

ID=16937828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57232350A Pending JPS59115623A (en) 1982-12-22 1982-12-22 Pll

Country Status (1)

Country Link
JP (1) JPS59115623A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230426U (en) * 1985-08-03 1987-02-24
JPH0221725A (en) * 1988-07-11 1990-01-24 Nec Corp External synchronizing clock pulse generating circuit
US6392497B1 (en) 2000-08-02 2002-05-21 Mitsubishi Denki Kabushiki Kaisha Phase-locked loop circuit with high lock speed and stability

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6230426U (en) * 1985-08-03 1987-02-24
JPH0221725A (en) * 1988-07-11 1990-01-24 Nec Corp External synchronizing clock pulse generating circuit
US6392497B1 (en) 2000-08-02 2002-05-21 Mitsubishi Denki Kabushiki Kaisha Phase-locked loop circuit with high lock speed and stability

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