KR100792042B1 - A spread spectrum clock generator - Google Patents

Abstract

A spread spectrum clock generator is provided to improve the peak power reduction effect of an output frequency and to easily change the design thereof. A spread spectrum clock generator(500) includes a phase frequency detector(510), a charge pump(520), a voltage controlled oscillator(530), a divider(540), and a waveform generator(550). The waveform generator applies a jitter component by directly applying a specific waveform to the power voltage of the voltage controlled oscillator. The specific waveform generated by the waveform generator is a triangular waveform. The waveform generator includes an operational transconductance amplifier.

Description

Spread Spectrum Clock Generator {A SPREAD SPECTRUM CLOCK GENERATOR}

1 is a block diagram illustrating an example of an SSCG 100 of a divider modulation scheme.

Fig. 2 is a diagram showing the area occupied by the Σ-Δ modulator 230 in the SSCG of the divider modulation scheme.

3 is a block diagram of an SSCG 300 of a conventionally proposed charge pump modulation scheme.

4 illustrates the basic idea of SSCG in accordance with the present invention.

FIG. 5 is a block diagram of an SSCG according to an embodiment of the present invention which actually implements the basic idea of the SSCG according to the present invention shown in FIG. 4; FIG.

6 shows a schematic diagram of an operational transconductance amplifier (OTA) used in a waveform generator of an SSCG in accordance with an embodiment of the present invention.

Fig. 7 shows the dBm spectrum of the output clock when there is no spread spectrum, and Fig. 8 shows the dBm spectrum of the output clock when there is a spread spectrum according to the present invention.

<Explanation of symbols for main parts of the drawings>

100 : SSCG of divider modulation method

110: Phase Frequency Detector (PFD)

120: charge pump (CP)

130: oscillator

140: Functional N-Divider

150: Σ-Δ modulator

160: reference clock

170: output clock (with spread)

200 : whole chip

210: Phase Locked Loop (PLL)

220: address generator

230: Σ-Δ modulator

300 : SSCG of charge pump modulation

310: phase frequency detector (PFD)

320: charge pump I (CP I)

330: Voltage Control Oscillator (VCO)

340: Programmable Divider

350: Programmable CP II

410: voltage controlled oscillator (VCO)

420: waveform generator

430: triangular waveform (generated by waveform generator)

440: VDD (which is the power supply voltage of the VCO)

450, 460, 470: Operational Transconductance Amplifier (OTA)

500 : SSCG (according to one embodiment of the present invention)

510: phase frequency detector (PFD)

520 charge pump (CP)

530: voltage controlled oscillator (VCO)

540: divider

550: Waveform Generator

560 loop filter

570: voltage control signal (Vctrl)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum clock generator (SSCG), and more specifically, a specific waveform, such as a triangular waveform, is directly applied to a power supply voltage of a voltage control oscillator (VCO) constituting the SSCG. By applying artificial jitter components, the structure is simpler than the conventional SSCG and the area is reduced, and the peak power reduction effect of the output frequency, which is an indicator of Electro Magnetic Interference (EMI), is improved. And an easy design change.

As the frequency of operation and increase in the number of data input bits between various information devices has been increased, high frequency clock signals generated in the VCO, which is an internal block of a phase locked loop (PLL), are required for timing data at the data transmission / reception stages between interfaces. Electromagnetic Interference (EMI) is prominent, which causes malfunctions in peripheral circuits, which causes side effects in transmission and reception of interface devices and data. Among various methods for reducing such EMI, Spread Spectrum Clock Generator (SSCG) is a method that can effectively reduce EMI by reducing the power density of the output frequency of the output signal by using spectrum spread of the output signal frequency. Known. SSCG is not only applied to high speed interface circuits in computer boards such as Serial Advanced Technology Attachment (II-II), but also widely used in computer peripherals and LCD panels.

Most commonly used SSCGs use Σ-Δ modulators and functional N-dividers to spread the spectrum of the output frequency by periodically changing the division ratio. Modulation method is used. 1 is a block diagram showing an example of an SSCG of a frequency division modulation method. The SSCG 100 of the divider modulation scheme having the structure shown in FIG. 1 can be easily spread by using the Σ-Δ modulator 150 and the functional N-divider 140 to adjust the division ratio. δ) and the modulating waveform, while the Σ-Δ modulator 150 and the functional N-divider 140, which are used for modulation, are complex digital circuits. It has the disadvantage of greatly increasing the total area of 100. FIG. 2 is a diagram illustrating an area occupied by a Σ-Δ modulator in an SSCG of a divider modulation scheme. 2, the phase locked loop (PLL) 210 and the address generator 220 determine how large the Σ-Δ modulator 230 occupies in the total area 200 when the divider modulation scheme is adopted. It can confirm by comparing with the area to occupy. Table 1 shows the general chip area of the SSCG of the divider modulation method. When designing the SSCG of the divider modulation method using a 0.18 um CMOS process from Table 1, the chip area is more than 1.00 mm × 1.00 mm. You can check it.

author fair Modulation method Chip Area (with Loop Filter) Wei-Ta Chen 0.18 um Σ-Δ modulation 1.00mm × 1.00mm Hyun Rok, Lee 0.18 um Σ-Δ modulation 0.94mm × 1.75mm Masaru kokubo 0.15 um Σ-Δ modulation 0.88mm × 0.48mm

In addition to the SSCG of the frequency division modulation method described above, SSCGs of various modulation methods have been studied. Among them, the SSCG of the charge pump modulating method adds only a charge pump to the structure of a general phase locked loop (PLL). It is expected to solve the area problem. 3 is a block diagram of the SSCG 300 of the conventionally proposed charge pump modulation scheme. As shown in FIG. 3, the SSCG 300 of the charge pump modulation scheme further includes a programmable charge pump II 350 in addition to the existing charge pump I 320. As mentioned above, although the charge pump modulation SSCG is expected to solve the area problem of the existing SSCG, the charge pump modulation SSCG proposed so far has some problems. First, it has a very complex structure because it is designed for too many applications, and therefore has a larger area than the existing SSCG. Second, since the diffusion ratio δ is adjusted by adjusting the fine current, the adjustment of the current is very sensitive to the operation of the circuit. Finally, it has a simple triangle modulation profile (Triangle Modulation Profile) has a problem that the power density by frequency at the maximum spreading frequency is larger than the average power density value.

The present invention has been proposed to solve the above problems, by applying a specific waveform, such as a triangular waveform directly to the power supply voltage of the voltage control oscillator (VCO) constituting the SSCG by applying an artificial jitter component, Its purpose is to provide an SSCG with simpler structure and reduced area than the existing SSCG, and to improve the effect of reducing the peak power of the output frequency, which is an indicator of electromagnetic interference, and to easily change the design.

Spread spectrum clock generator (SSCG) according to a feature of the present invention for achieving the above object,

Spread Spectrum Clock Generator including Phase Frequency Detector (PFD), Charge Pump (CP), Voltage Control Oscillator (VCO) and Divider ,

The voltage controlled oscillator further includes a waveform generator for applying an artificial jitter component by directly applying a specific waveform to the power supply voltage.

According to another aspect of the present invention, the SSCG is characterized in that the specific waveform generated by the waveform generator is a triangular wave form.

The SSCG according to another aspect of the present invention is characterized in that the waveform generator includes an operational transconductance amplifier (OTA).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a view for explaining the basic idea of the SSCG according to the present invention. As shown in FIG. 4, the SSCG according to the present invention, unlike the conventional divider modulation method and the charge pump modulation method, uses the OTAs 450, 460, and 470 to the power supply voltage VDD 440 applied to the VCO 410. The basic idea is to implement SSCG by directly applying the triangular waveform 430 generated by the waveform generator 420 composed of In other words, an artificial jitter component is applied to a PLL, which is a basic concept of SSCG, to obtain a spread spectrum, thereby directly applying an artificial triangular waveform to the power supply voltage VDD 440 of the VCO 410, which is an important block in generating a frequency of the PLL. There is that originality.

FIG. 5 is a diagram showing an overall block diagram of an embodiment of the SSCG which actually implements the basic idea of the SSCG according to the present invention shown in FIG. 4. As shown in FIG. 5, the SSCG 500 according to the present invention includes a phase frequency detector (PFD) 510, a charge pump (CP) 520, a voltage controlled oscillator (VCO) 530, and a divider 540. In particular, it further includes a waveform generator 550 for applying a specific waveform directly to the power supply voltage to the voltage controlled oscillator 530 to apply an artificial jitter component.

5, it can be seen that the SSCG according to the present invention can be divided into two parts, a general phase locked loop (PLL) block and a modulation circuit block. To implement the SSCG without affecting the basic operation of the PLL trying to lock phase, the waveform generator 550 implements a triangular waveform with a voltage width of 0.05 mV to 200 mV, and then the power supply voltage of the VCO 510. 1.8V) directly. The applied waveform changes the amount of the current source bias voltage at the bottom of VDD in proportion to the modulation period and voltage width. The frequency generated through the displacement of the voltage and current is changed in the Down direction or the Up direction within a predetermined amount with respect to the reference frequency. As such, the frequency up or down is a constant period of the Vctrl signal 570 for controlling the frequency of the VCO 530 while passing through the phase frequency detector 510, the charge pump 520, the loop filter (560) Change to a sinusoidal shape. In this way, the modulation waveform applied directly to the power supply voltage of the VCO 530 affects the Vctrl signal 570 through a feedback loop and again changes the output frequency according to the modulation range of the VCO 530. do.

Referring to the operation principle of the SSCG according to an embodiment of the present invention shown in FIG. 5 in more detail. The operating principle of the SSCG according to an embodiment of the present invention shown in FIG. 5 is a VCO by applying a triangular modulation profile (Triangular Modulation Profile) to the VDD of a 3-stage ring type VCO (530). Shake the VDD of 530 to generate a spread spectrum clock. In this way, the VCO 530 generates a 1.2 to 3% down spread spectrum clock around 1.5 GHz according to the modulation profile. The generated clock is modulated into a signal having the same frequency as the reference clock by using a 20-divider 540 configured as a TSPC DFF (True Single Phase Clocked D Flip-Flop). Ref_clk = 75 MHz). The PFD 510 compares the frequency of the reference clock and the feedback clock to apply an up or down signal to the charge pump 520. Initially, the SSCG 500 continuously generates an Up signal up to a locked voltage (0.85V) and a frequency (1.5 GHz) of the PLL, thereby bringing the SSCG 500 close to a fixed state. Thereafter, a periodic signal of up or down is generated according to the modulation waveform of VDD, thereby generating a control voltage waveform having a change of 30 mV from peak to peak. For this operation, the design of the structure of the VCO 530 is important. It is important to design the spread spectrum clock within a certain range without sudden frequency fluctuations in the change of the Vctrl signal 570, and when the spread spectrum clock is generated, the voltage ripples near the center of the gain curve of the VCO 530. It is also important to design it to be ripple. As a result, the modulation waveform of VDD shakes the voltage value Vctrl 570 that controls the operating frequency of the VCO 530, thereby generating a spread spectrum clock.

Next, referring to FIG. 6, a waveform generator including an operational transconductance amplifier (OTA) and an OTA will be described in more detail. 6 is a schematic diagram of an operational transconductance amplifier (OTA) used in a waveform generator of an SSCG in accordance with an embodiment of the present invention. The waveform generator constructed using the OTA shown in FIG. 6 can generate a square wave through a feedback loop of the circuit itself without external input, and integrates an integral element of a capacitor configured therein with respect to the generated square wave. By using this, triangular waveforms can be generated. At this time, various modulation waveforms having a voltage in the range of 0.01 to 200 mV and a period in the range of 2 to 30 us can be obtained by adjusting the current and capacitance values flowing in the circuit. Due to this feature, the present structure can be applied not only to the frequency of the 1.5 GHz band corresponding to SATA-II but also to the frequency band of several hundred MHz.

Next, the dBm spectrum of the output clock when there is no spread spectrum and the dBm spectrum of the output clock when there is a spread spectrum according to the present invention will be compared with reference to FIGS. 7 and 8. Fig. 7 shows the dBm spectrum of the output clock when there is no spread spectrum, and Fig. 8 shows the dBm spectrum of the output clock when there is a spread spectrum according to the present invention. From Fig. 7, it can be seen that in the absence of the spread spectrum, there are almost no frequency components appearing in the sideband around 1.5 Hz, and have a value of about 30 dBm at 1.5 Hz. In comparison, from Fig. 8, when there is a spread spectrum according to the present invention (down spread spectrum modulation of 1.5%), it has a value of about 20 dBm, and the effect of improving EMI through SSCG according to the present invention is about 10 dBm. I can confirm that it is.

Table 2 summarizes the performance of the SSCG according to the present invention. Briefly summarized, the SSCG according to the present invention was designed using Hynix's 0.18 μm CMOS process, and by applying a modulation waveform to VDD, a spread spectrum waveform with 1.5 to 3% down frequency variation was obtained. . In addition, the power consumption was 32.4 mA at a power supply voltage of 1.8V.

SSCG frequency 1.5 GHz Process technology Hynix 0.18 um CMOS Modulation method Modulation on VCO Modulating waveform 30 to 33 kHz Frequency Deviation 1.5-3% down Jitter (Non-SSC) 54 ps Loop band 608 kHz Phase margin 65.4 degrees Power supply voltage 1.8 V Power consumption 32.4 mW

As described above, the SSCG proposed by the present invention can be roughly divided into a phase locked loop (PLL) block and a modulation block. According to the state of the art, the PLL block can be integrated within 400 μm × 400 μm. Therefore, considering the number of devices and the size of capacitors constituting the waveform generator, the entire SSCG according to the present invention is sufficiently integrated within 600 μm × 600 μm. I think it will be lost. This area corresponds to a 36% area reduction compared to the total area (1.00mm × 1.00mm) occupied by the existing SSCG.

In summary, according to the SSCG according to the present invention, although the Hershey-Kiss modulation waveform for uniform frequency-specific power density is not applied, the edge frequency and center frequency of the spread spectrum clock (SSC) are applied. The average value of) is confirmed to secure about 10dB of EMI reduction. Therefore, according to the present invention, by reducing the area by 36% compared to the existing SSCG that achieves the same size EMI reduction, it is possible to increase the number of finished products that can be obtained on one wafer compared to other products, thereby Lower product prices are expected to contribute significantly to price competitiveness in the market.

The present invention described above may be variously modified or applied by those skilled in the art, and the scope of the technical idea according to the present invention should be defined by the following claims.

According to the present invention, by applying a specific waveform directly to the power supply voltage of the voltage controlled oscillator (VCO) constituting the SSCG by applying an artificial jitter component, it is implemented in a simpler structure and reduced area than the conventional SSCG, The peak power reduction effect of the output frequency, which is an indicator, can be improved and a design change can be easily provided.

Claims (3)

Spread Spectrum Clock Generator including Phase Frequency Detector (PFD), Charge Pump (CP), Voltage Control Oscillator (VCO) and Divider , A waveform generator for applying an artificial jitter component by applying a specific waveform directly to the power supply voltage to the voltage controlled oscillator, A spread spectrum clock generator wherein the specific waveform generated by the waveform generator is a triangular wave form. delete The method of claim 1, The waveform generator includes an operational transconductance amplifier (OTA).

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