JPS59114854A - Laminated integrated circuit element - Google Patents

Laminated integrated circuit element

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Publication number
JPS59114854A
JPS59114854A JP57223056A JP22305682A JPS59114854A JP S59114854 A JPS59114854 A JP S59114854A JP 57223056 A JP57223056 A JP 57223056A JP 22305682 A JP22305682 A JP 22305682A JP S59114854 A JPS59114854 A JP S59114854A
Authority
JP
Japan
Prior art keywords
film
semiconductor layer
thermal conductivity
integrated circuit
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57223056A
Other languages
Japanese (ja)
Inventor
Toshiaki Miyajima
利明 宮嶋
Masayoshi Koba
木場　正義
Atsushi Kudo
淳 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
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Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP57223056A priority Critical patent/JPS59114854A/en
Publication of JPS59114854A publication Critical patent/JPS59114854A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To enable to form a single crystal semiconductor layer of homogeneity and a large area and thus obtain a laminated integrated circuit element of good quality by a method wherein an insulation film interposed between a semiconductor layer is made to act heat insulation by using the laminated integration of a dielectric of a small thermal conductivity. CONSTITUTION:An Mo film 13 is deposited on a substrate 11 and then patterned to an electrode or wiring form. Next, an SiO2 film 15 of a relatively small thermal conductivity is so formed on the semiconductor layer after wiring that the thickness in the upper part of the Mo electrode 13 becomes at least 1mum. Amorphous Si 21 is formed thereon to approx. 0.5mum, and thereafter the Si film 21 is single-crystallized by the irradiation of an Ar laser. Since the thermal conductivity of the SiO2 film is relatively small, there is heat shielding effect, it is sufficient that the influence by a conductor on the surface of a semiconductor hardly appear, and the distribution of surface temperatures can be made more uniform. The uniformity of the temperature distribution of the amorphous Si can be contrived, and the single crystal of a uniform film thickness and a large grain diameter can be prepared. In addition to the SiO2 film, a dielectric material having the value of thermal conductivity at 0.02J/cm.sec.deg. or less can be utilized.

Description

【発明の詳細な説明】 く技術分野〉 本発明は積層集積回路素子に関し、特に積層した半導体
層間に絶縁膜を介挿し、半導体層にエネルギービームを
照射してアニールする積層集積回路素子に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a laminated integrated circuit device, and more particularly to a laminated integrated circuit device in which an insulating film is interposed between stacked semiconductor layers and the semiconductor layers are annealed by irradiating the semiconductor layers with an energy beam.

〈従来技術〉 近年、半導体集積回路装置を一層高密度化するべく、三
次元に半導体層を積層した素子の開発が試みられている
。<Prior Art> In recent years, in order to further increase the density of semiconductor integrated circuit devices, attempts have been made to develop elements in which semiconductor layers are stacked three-dimensionally.

第１図は従来から提案されている積層高密度集積回路素
子の断面図で、実際には更に多層に積層するが、図が複
雑になるのを避けるため半導体層１０．２０を２層に積
層した例を示す。半導体基板１１．２１に不純物領域１
２．２２を形成し、適宜導電体１３によって電気的接続
を施こした各半導体層１０及び２０は、絶縁層３０を介
して積層されている。Figure 1 is a cross-sectional view of a stacked high-density integrated circuit device that has been proposed in the past.In reality, more layers are stacked, but to avoid complicating the diagram, two semiconductor layers 10 and 20 are stacked. Here is an example. Impurity region 1 on semiconductor substrate 11.21
The semiconductor layers 10 and 20, which are electrically connected to each other by conductors 13 as appropriate, are laminated with an insulating layer 30 in between.

上記積層構造の集積回路素子を製造する場合、回路を作
成した第１半導体層ＩＯ上に全面に絶縁膜３０を被着し
、次に第２半導体層２０のためにポリシリコン或いは非
晶質シリコン２１膜を形成して液膜２１を単結晶化し、
回路素子を作成する。When manufacturing an integrated circuit element having the above-mentioned laminated structure, an insulating film 30 is deposited on the entire surface of the first semiconductor layer IO on which a circuit is formed, and then polysilicon or amorphous silicon is deposited for the second semiconductor layer 20. 21 film is formed and the liquid film 21 is made into a single crystal,
Create circuit elements.

ポリシリコン或いは非晶質シリコン膜を単結晶化するた
めにアニール処理が行われるが、従来から電気炉アニー
ルによる方法と、光、電子或いはイオン等を照射するエ
ネルギービームアニールによる方法とがある。後者のエ
ネルギービームアニールによる方法は、前者の電気炉ア
ニールに比べ一般にアニールに要する処理時間が短かい
という特性がある。Annealing treatment is performed to single-crystallize polysilicon or amorphous silicon films, and conventional methods include electric furnace annealing and energy beam annealing in which light, electrons, ions, etc. are irradiated. The latter method using energy beam annealing has a characteristic that the processing time required for annealing is generally shorter than the former method of electric furnace annealing.

処で順次半導体層を積層して素子を構成する場合、下層
の半導体層に（起席既に回路素子が形成されている。従
ってこのような下層半導体層にとってはアニールされる
ことは好ましくない。When an element is constructed by sequentially stacking semiconductor layers, a circuit element is already formed in the lower semiconductor layer. Therefore, it is not preferable for such a lower semiconductor layer to be annealed.

エネルギービームアニール法では上述のようにアニール
時間が短かいという特性があり、これはまた素子全体が
均一な温度になり難いことである。As mentioned above, the energy beam annealing method has a characteristic that the annealing time is short, and this also makes it difficult to achieve a uniform temperature throughout the device.

このようなことを利用し、アニール時間を熱が膜の深さ
方向へ伝搬する時間より短かくすることで一ヘ下部半導
体層に熱的な影響を与えることなく、アニールしたい上
部半導体層のみ温度を上げてアニールすることができる
。By making use of this fact and making the annealing time shorter than the time it takes for heat to propagate in the depth direction of the film, the temperature of only the upper semiconductor layer to be annealed can be reduced without thermally affecting the lower semiconductor layer. can be annealed by increasing the

しかしこの種の積層集積回路素子は、通常アニールすべ
き半導体層の下部には既に回路素子が作り込まれており
、特に半導体層表面には金属やポリシリコン等の熱伝導
性にすぐれた導電体によって電極及び配線が形成されて
いる。従ってこのような積層半導体層をアニールする場
合、特に処理時間が短い場合には下部半導体の表面状態
、例えば導電体がある部分と無い部分でアニールすべき
半導体層′の温度上昇が異なる事態が生じる。However, in this type of laminated integrated circuit device, circuit elements are already built in under the semiconductor layer that should be annealed, and in particular, the surface of the semiconductor layer is made of a conductor with excellent thermal conductivity such as metal or polysilicon. Electrodes and wiring are formed by. Therefore, when annealing such laminated semiconductor layers, especially when the processing time is short, the temperature rise of the semiconductor layer to be annealed may differ depending on the surface condition of the lower semiconductor, for example, where there is a conductor and where there is no conductor. .

例えば第２図に示すようにシリコン基板１１内に通常の
方法で半導体素子を作り込み、表面にはＭｏ電極１３を
１μｍの厚さに堆積する。その後表面全体が平坦になる
よう（乙且つＭｏ電極Ｉ３がない部分での厚さが１．５
μｍになるように５ｉ０２膜１４を形成し、さらにその
上に非晶質シリコン層２１を０．５μｍの厚さに形成し
、該非晶質シリコン膜２１に出力１５Ｗで１００μｍ径
のＡｒレーザーを照射してアニ・−ルする。Ｍｏ電極１
３がない部分での非晶質シリコン２Ｉの表面温度が１０
００℃になった時の非晶質シリコン全体の温度分布を第
３図に示す。第３図より、ＭＯ電極１３上部の非晶質シ
リコン表面では、熱伝導率の大きいＭｏ電極の影響を受
けてＭｏ電極のない部分に比べ最高１５０℃程度温度の
低い部分が生じる。For example, as shown in FIG. 2, a semiconductor element is formed in a silicon substrate 11 using a conventional method, and a Mo electrode 13 is deposited on the surface to a thickness of 1 μm. After that, the entire surface was made flat (and the thickness of the part without Mo electrode I3 was 1.5
A 5i02 film 14 is formed to have a thickness of μm, and an amorphous silicon layer 21 is further formed on it to a thickness of 0.5 μm, and the amorphous silicon film 21 is irradiated with an Ar laser having a diameter of 100 μm and an output of 15 W. and then ani-le. Mo electrode 1
The surface temperature of amorphous silicon 2I in the part without 3 is 10
FIG. 3 shows the temperature distribution of the entire amorphous silicon when the temperature reached 00°C. From FIG. 3, on the amorphous silicon surface above the MO electrode 13, under the influence of the Mo electrode having a high thermal conductivity, there is a portion whose temperature is at most 150° C. lower than the portion without the Mo electrode.

この状態でアニールを続けるとＭｏ電極のある部分とな
い部分で半導体層２１のアニールのされ方が異なり、粒
径の大きい単結晶を得ることが難かしく、また単結晶の
膜質も均質なものにならず積層構造の集積回路素子基板
として利用するには問題があった。If annealing is continued in this state, the semiconductor layer 21 will be annealed differently depending on the part with the Mo electrode and the part without, making it difficult to obtain a single crystal with a large grain size, and the film quality of the single crystal will not be uniform. However, there was a problem in using it as an integrated circuit element substrate with a laminated structure.

〈発明の目的〉 本発明は上記従来の積層集積回路素子の問題点に鑑みて
なされたもので、エネルギービーム照射によってアニー
ルを行う際、下部半導体層の表面状態に関係なくアニー
ルすべき半導体層表面の温度分布が均一になるように、
半導体層間に介挿する絶縁膜の材質及び膜厚を選択し、
均質で大面積の単結晶半導体層を得ることができる積層
集積回路素子を提供することである。<Object of the Invention> The present invention has been made in view of the above-mentioned problems of the conventional laminated integrated circuit elements. so that the temperature distribution of
Select the material and thickness of the insulating film to be inserted between the semiconductor layers,
An object of the present invention is to provide a laminated integrated circuit element that can obtain a homogeneous, large-area single crystal semiconductor layer.

〈実施例〉 第４図は本発明による一実施例の要部を示す素子断面図
で、図中第２図と同一部分は同一符号で示す。<Embodiment> FIG. 4 is a sectional view of an element showing essential parts of an embodiment according to the present invention, and the same parts as in FIG. 2 are designated by the same reference numerals.

シリコン基板１１内に通常の方法で半導体素子を作り込
み、続いて回路動作を可能にするべく基板表面に厚さＩ
μｍ程度にＭｏ膜１３を堆積し、該Ｍｏ膜１３を電極或
いは配線形状にパターニングする。Semiconductor elements are fabricated in a silicon substrate 11 by a conventional method, and then a thickness of I is formed on the surface of the substrate to enable circuit operation.
A Mo film 13 is deposited to a thickness of about μm, and the Mo film 13 is patterned into an electrode or wiring shape.

次に上部半導体層との絶縁をはかるために、配線後の半
導体層上に熱伝導率の比較的小さい５ｉ０２膜１５を形
成する。このとき５ｉ０２膜１５の膜厚はＭｏ電極１３
上部での厚さが少なくとも１μｍになるように充分厚く
スパッタリングによって作成する。５１０２膜１５を絶
縁膜として、上部に非晶質シリコン２１を０．５μｍ程
度に形成し、その後出力１５Ｗ、１００μｍ径のＡｒレ
ーザーを照射してシリコン膜２１を単結晶化する。Next, in order to insulate the semiconductor layer from the upper semiconductor layer, a 5i02 film 15 having a relatively low thermal conductivity is formed on the semiconductor layer after wiring. At this time, the thickness of the 5i02 film 15 is the same as that of the Mo electrode 13.
It is made sufficiently thick by sputtering so that the thickness at the top is at least 1 μm. Using the 5102 film 15 as an insulating film, amorphous silicon 21 is formed on the top to a thickness of about 0.5 μm, and then an Ar laser with an output of 15 W and a diameter of 100 μm is irradiated to convert the silicon film 21 into a single crystal.

上記レーザーアニールの過程において、Ｍｏ電極１３が
ない部分の上に位置する非晶質シリコン表面の温度が１
０００℃になったときの非晶質シリコン表面全体の温度
分布を第５図に示す。同図から明らかなようにＭｏ電極
１３がある部分とない部分とでの非晶質シリコン膜２１
の表面温度差を５・０℃以内におさめることができ、表
面全体としての温度分布のバラツキを小さくすることが
できる。これは半導体層表面を被うＳ　ｉ０２膜の熱伝
導率が比較的小さいため、たとえ表面からレーザービー
ムを照射して加熱を行っても、熱遮蔽効果があって半導
体表面の導電体による影響がほとんど現われずに済み表
面温度分布をより均一にすることかできる。尚５ｉ０２
膜表面の温度分布のバラツキをアニール処理に支障がな
い５０℃以内にするためには膜厚として１μｍ以上にす
ることが望ましい。In the laser annealing process, the temperature of the amorphous silicon surface located on the part where the Mo electrode 13 is not increased to 1
FIG. 5 shows the temperature distribution over the entire amorphous silicon surface when the temperature reached 000°C. As is clear from the figure, the amorphous silicon film 21 has parts with and without Mo electrodes 13.
It is possible to keep the surface temperature difference within 5.0°C, and it is possible to reduce the variation in temperature distribution over the entire surface. This is because the thermal conductivity of the Si02 film that covers the surface of the semiconductor layer is relatively low, so even if the surface is heated by irradiating a laser beam, it has a heat shielding effect and is not affected by the conductor on the surface of the semiconductor. The surface temperature distribution can be made more uniform with almost no appearance. Sho 5i02
In order to keep the variation in temperature distribution on the film surface within 50° C., which does not interfere with the annealing process, it is desirable that the film thickness be 1 μm or more.

特にレーザーアニールのように短時間でアニール処理し
得る場合でも、非晶質シリコン或いはポリシリコン膜の
温度分布の均一化を図ることができ、膜厚が均一で粒径
の大きい単結晶を作成することができる。In particular, even when annealing can be performed in a short time such as laser annealing, it is possible to make the temperature distribution of an amorphous silicon or polysilicon film uniform, creating a single crystal with uniform film thickness and large grain size. be able to.

上記実施例はＭｏ電極上部にＳ　ｉ０２膜を堆積したが
、熱伝導率が０．０２１７ｃｍｍ　ｓｅｃ　ｓｄｅｇ以
下の値をもつ誘電体、例えばＰＳＧ等の材料を利用する
ことができ、また半導体層表面の導電体はＭｏに限らず
、他の金属或いは金属のシリサイド、ポリシリコン等導
電性材料であってもよい。In the above example, a Si02 film was deposited on the top of the Mo electrode, but a dielectric material with a thermal conductivity of 0.0217 cm sec sdeg or less, such as PSG, can be used. The conductor is not limited to Mo, but may be other metals, metal silicides, polysilicon, or other conductive materials.

また上記実施例では、Ａｒレーザーアニール処理時に、
アニールすべき非晶質シリコン膜の表面が露出していた
か、非晶質シリコン膜上部に５ｉ０２膜やＳｉ３Ｎ４膜
、さらにはこれらの積層膜等を形成した後アニールを行
なってもよいし、アニール法としてはＡｒ　レーザーア
ニールに限らず、他のレーザーアニール、光アニール、
電子ビームアニール、イオンビームアニール等、エネル
ギービームアニールであればその方法は問わない。Furthermore, in the above embodiment, during Ar laser annealing treatment,
The surface of the amorphous silicon film to be annealed may be exposed, or annealing may be performed after forming a 5i02 film, Si3N4 film, or a stacked film of these on top of the amorphous silicon film, or annealing may be performed after the surface of the amorphous silicon film to be annealed is exposed. This is not limited to Ar laser annealing, but also other laser annealing, optical annealing,
Any energy beam annealing method may be used, such as electron beam annealing or ion beam annealing.

〈効果〉 以上詳説した如く、本発明によれは半導体層間に介挿す
る絶縁膜に熱伝導率の小さい誘電体積層集積を用いて断
熱作用をさせることにより積層集積回路素子の半導体層
をエネルギービームでアニールする際、面内の温度分布
を均一にすることが可能となり、その結果均質で大面積
の単結晶半導体層の形成が可能となり、良質の積層集積
回路素子を得ることができる。<Effects> As explained in detail above, according to the present invention, the semiconductor layers of the laminated integrated circuit element are exposed to energy beams by using a dielectric laminated stack with low thermal conductivity to provide heat insulation to the insulating film interposed between the semiconductor layers. When annealing is performed, it is possible to make the in-plane temperature distribution uniform, and as a result, it is possible to form a homogeneous, large-area single crystal semiconductor layer, and a high-quality laminated integrated circuit element can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は積層集積回路素子の要部断面図、第２図はエネ
ルギービームアニールを行なう時の素子断面の模式図、
第３図は第２図の試料にＡｒレーザーを照射したときの
非晶質シリコン表面全体の温度分布図、第４図は本発明
の一実施例を説明する素子断面図、第５図は同実施例に
Ａｒレーザーを照射したときの非晶質シリコン全体の温
度分布図である。 １０・・・下部半導体層、２０・・・上部半導体層、１
１・・・シリコン基板、１３・・・Ｎｏ電極配線、２】
・・・非晶質シリコン膜、１５・・・ＳｉＯ２膜。Figure 1 is a cross-sectional view of the main parts of a laminated integrated circuit element, Figure 2 is a schematic diagram of a cross-section of the element during energy beam annealing,
FIG. 3 is a temperature distribution diagram of the entire amorphous silicon surface when the sample in FIG. 2 is irradiated with an Ar laser, FIG. FIG. 2 is a temperature distribution diagram of the entire amorphous silicon when an example is irradiated with an Ar laser. 10... Lower semiconductor layer, 20... Upper semiconductor layer, 1
1... Silicon substrate, 13... No electrode wiring, 2]
...Amorphous silicon film, 15...SiO2 film.

Claims (1)

【特許請求の範囲】[Claims] １）素子形成した半導体層を、誘電体層を介して少なく
とも２層以上積層し、半導体層にエネルギービームアニ
ールを施こしてなる積層集積回路素子において、導電体
によって電極配線した半導体層上に、少なくとも導電体
上での膜厚が１μｍ以上で、且つ熱伝導率が０．０２　
Ｊ１０ｎ＠ｓｅｃｔｄｅｇ以下の誘電体を半導体間の絶
縁膜として介挿してなることを特徴とする積層集積回路
素子。1) In a multilayer integrated circuit device in which at least two or more device-formed semiconductor layers are stacked with dielectric layers interposed therebetween and energy beam annealing is applied to the semiconductor layers, on the semiconductor layer electrodes are wired using a conductor, The film thickness on the conductor is at least 1 μm or more, and the thermal conductivity is 0.02
A laminated integrated circuit element characterized in that a dielectric material of J10n@sectdeg or less is inserted as an insulating film between semiconductors.
JP57223056A 1982-12-21 1982-12-21 Laminated integrated circuit element Pending JPS59114854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57223056A JPS59114854A (en) 1982-12-21 1982-12-21 Laminated integrated circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57223056A JPS59114854A (en) 1982-12-21 1982-12-21 Laminated integrated circuit element

Publications (1)

Publication Number Publication Date
JPS59114854A true JPS59114854A (en) 1984-07-03

Family

ID=16792141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57223056A Pending JPS59114854A (en) 1982-12-21 1982-12-21 Laminated integrated circuit element

Country Status (1)

Country Link
JP (1) JPS59114854A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57106158A (en) * 1980-12-24 1982-07-01 Toshiba Corp Integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57106158A (en) * 1980-12-24 1982-07-01 Toshiba Corp Integrated circuit

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