JPS59114831A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS59114831A
JPS59114831A JP57223802A JP22380282A JPS59114831A JP S59114831 A JPS59114831 A JP S59114831A JP 57223802 A JP57223802 A JP 57223802A JP 22380282 A JP22380282 A JP 22380282A JP S59114831 A JPS59114831 A JP S59114831A
Authority
JP
Japan
Prior art keywords
metal plate
insulating substrate
solder
outer container
linear expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57223802A
Other languages
Japanese (ja)
Inventor
Shuhei Tanaka
修平 田中
Toshiaki Hirama
利昭 平間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP57223802A priority Critical patent/JPS59114831A/en
Publication of JPS59114831A publication Critical patent/JPS59114831A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
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    • H01L2924/01047—Silver [Ag]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To facilitate the uniforming of thickness of a solder film, and thickening the solder film and the overall thickness, thereby to increase adhesive strength, and to improve conductivity and reliability by putting together an insulating substrate and a thin metallic plate or conductive film having the nearly same linear expansion coefficient as said substrate respectively through solder and sticking them to a metallic plate of an outer container. CONSTITUTION:An alumina substrate 1 carrying a part 3 and forming a conductive film 5 of silver-palladium group on its back surface and a metallic or conductive thin plate 6 having a linear expansion coefficient of 7X10<-6>/ deg.C (e.g. Kovar) are stuck together through Sn-Pb autectic solder 4-1, and said metallic or conductive thin plate 6 is stuck to a metallic plate 2 which is part of an outer container through eutectic solder 4-2.

Description

【発明の詳細な説明】 本発明は電子回路基板の裏面を金属ケースに接続した構
造を有する混成集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit having a structure in which the back side of an electronic circuit board is connected to a metal case.

従来、銅、しんちゅう等の金属で外装容器を形成する場
合、第１図に示すように、アルミナ等の絶縁基板１の上
面に塔載部品３を増付けた厚膜回路パターンを設け、裏
面に上記外装容器の金属板部２とはんだ４で接着するた
めに全面べたの銀−パラジウム系厚膜導体５を設けてい
た。しかし。Conventionally, when forming an outer container from metal such as copper or brass, as shown in FIG. A solid silver-palladium thick film conductor 5 was provided on the entire surface to be bonded to the metal plate portion 2 of the outer container with solder 4. but.

５ｎ−ｐｂ共晶はんだで接続した場合、金属板２と絶縁
基板１０線膨張係数の差が太きいと第２図のようにそっ
た構造にできあがる上に、その後、装置のおかれる環境
条件、特に温度変化によって常に応力が加えられている
。このため、絶縁基板１のわれ、クランクの発生、ばん
だ４のクリープ、さらには破壊等が起き易（、信頼度上
問題があった。When connecting with 5n-pb eutectic solder, if the difference in the linear expansion coefficients of the metal plate 2 and the insulating substrate 10 is large, a curved structure as shown in Fig. 2 will be created. In particular, stress is constantly applied due to temperature changes. For this reason, the insulating substrate 1 is prone to cracking, cracking, creeping of the solder 4, and even destruction (and there are problems in terms of reliability).

また、これらの応力を減少させるために、はんだ４の厚
さを大きくして、はんだ４をクッションとして利用し、
金属板２による応力を絶縁基板１になるべく伝えないよ
うにする方法があるが、はんだ４を厚くすることにより
、その膜厚を均一にすることが困難なこと、また、膜を
厚くすること自体が困囃であり、製造コストが増大する
欠点があった。In addition, in order to reduce these stresses, the thickness of the solder 4 is increased and the solder 4 is used as a cushion.
There is a method to prevent the stress caused by the metal plate 2 from being transmitted to the insulating substrate 1 as much as possible, but by making the solder 4 thicker, it is difficult to make the film thickness uniform, and making the film thicker itself is difficult. However, there were drawbacks such as difficulty in performance and increased manufacturing costs.

本発明はこれらの欠点を除去するため、絶縁基板とほぼ
等しい線膨張係数を有する薄い金属板または導電膜を１
個または複数個をそれぞれはんだを介して重ね合わせて
外装容器の金属板と接着したことを特徴としたものであ
る。In order to eliminate these drawbacks, the present invention uses a thin metal plate or a conductive film having a coefficient of linear expansion approximately equal to that of the insulating substrate.
It is characterized in that one or more pieces are stacked one on top of the other via solder and bonded to the metal plate of the outer container.

第３図は本発明の実施例で１部品３を塔載し。FIG. 3 shows an embodiment of the present invention in which one part 3 is mounted on the tower.

裏面に銀−パラジウム系導体膜５を形成したアルミナ基
板１と、線膨張係数か７　Ｘ　１０−’　／’Ｃの金属
又は導電体薄板（例えばコバール）とをＳ。−Ｐｂ共晶
はんだ４−２で、また前記金属又は導電体の薄板６と外
装容器の一部をなす金属板２との間を共晶はんだ４−２
で接着している。An alumina substrate 1 with a silver-palladium-based conductor film 5 formed on its back surface and a metal or conductor thin plate (for example, Kovar) having a linear expansion coefficient of 7 x 10-'/'C are made of S. -Pb eutectic solder 4-2, and the eutectic solder 4-2 is used to connect the metal or conductor thin plate 6 and the metal plate 2 forming a part of the outer container.
It is attached with.

第４図は本発明の他の実施例で、金属又は導電体の薄板
６を６−１．６−２の２枚重ね、かつアルミナ基板１の
側の前記薄板６−１は外装容器の１部をなす金属板２の
側の薄板６−２の２倍の厚みになっている。FIG. 4 shows another embodiment of the present invention, in which two thin plates 6-1 and 6-2 of metal or conductor are stacked, and the thin plate 6-1 on the alumina substrate 1 side is one of the thin plates 6-1 and 6-2 of the outer container. The thickness is twice that of the thin plate 6-2 on the side of the metal plate 2 forming the section.

発明による絶縁基板と外装容器の金属板との接着は、は
んだ膜厚が均一になること及びはんだと総厚を厚くする
ことが比較的安価に、かつ容易に実現でき、接着強度が
増大し、熱伝導性もよ（なり信頼度が向上する。In the bonding between the insulating substrate and the metal plate of the outer container according to the invention, it is possible to make the solder film uniform in thickness and increase the total thickness of the solder at a relatively low cost and easily, and the bonding strength is increased. It also has good thermal conductivity (which improves reliability).

また、絶縁基板の裏面導体を接地として利用した場合に
は、接地が金属板と均一にかつ密に形成された構造とな
るため、電気的性能のばらつきが小さい混成集積回路が
実現できる。Further, when the back conductor of the insulating substrate is used as a ground, the structure is such that the ground is formed uniformly and densely with the metal plate, so a hybrid integrated circuit with small variations in electrical performance can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は従来の混成集積回路の断面図、第３
図及び第４図は本発明の実施例を示す一部の断面図であ
る。 １：アルミナ基板、２：外装容器の一部となる銅板、３
：塔載部品、４：はんだ、５：裏面導体。 ６：薄板。 第１図　　　　　第２図 第３図　　　　　　第４図Figures 1 and 2 are cross-sectional views of conventional hybrid integrated circuits;
FIG. 4 is a partial sectional view showing an embodiment of the present invention. 1: Alumina substrate, 2: Copper plate that becomes part of the outer container, 3
: Mounting component, 4: Solder, 5: Back conductor. 6: Thin plate. Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] （１）　　絶縁基板上に電子回路を形成した混成集積回
路で、上記絶縁基板の裏面に導体層を形成し。 該裏面導体層と外装容器の一部である金属板との接続に
関し、該絶縁基板とほぼ等しい線膨張係数を有する金属
板または導電膜またはその組合わせを１個または複数個
それぞれはんだを介して外装容器の金属板部と接着した
ことを特徴とする混成集積回路装置。(1) A hybrid integrated circuit in which an electronic circuit is formed on an insulating substrate, and a conductor layer is formed on the back surface of the insulating substrate. Regarding the connection between the back conductor layer and a metal plate that is a part of the outer container, one or more metal plates or conductive films, or a combination thereof, each having a linear expansion coefficient approximately equal to that of the insulating substrate, are connected via solder. A hybrid integrated circuit device characterized in that it is bonded to a metal plate portion of an outer container. （２）絶縁基板上に電子回路を形成した混成集積回路で
、上記絶縁基板の裏面に導体層を形成し。 該裏面導体層と外装容器の一部である金属板との接続に
関し、薄い金属板または薄い導電膜を。 絶縁基板側は、絶縁基板の線膨張係数に近い材料を外装
容器の金属板部は、金属板部の線膨張係数に近い材料を
使用し、徐々に線膨張係数を変え前記金属板または導電
膜またはその組合せを１個または複数個それぞれはんだ
を介して外装容器の金属板部と接着したことを特徴とす
る混成集積回路装置。(2) A hybrid integrated circuit in which an electronic circuit is formed on an insulating substrate, and a conductor layer is formed on the back surface of the insulating substrate. Regarding the connection between the back conductor layer and the metal plate that is part of the outer container, a thin metal plate or a thin conductive film is used. For the insulating substrate side, use a material with a linear expansion coefficient close to that of the insulating substrate.For the metal plate portion of the outer container, use a material close to the linear expansion coefficient of the metal plate portion, and gradually change the linear expansion coefficient to the metal plate or conductive film. A hybrid integrated circuit device characterized in that one or more of these combinations are bonded to a metal plate portion of an outer container via solder.
JP57223802A 1982-12-22 1982-12-22 Hybrid integrated circuit Pending JPS59114831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57223802A JPS59114831A (en) 1982-12-22 1982-12-22 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57223802A JPS59114831A (en) 1982-12-22 1982-12-22 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS59114831A true JPS59114831A (en) 1984-07-03

Family

ID=16803944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57223802A Pending JPS59114831A (en) 1982-12-22 1982-12-22 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59114831A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0921716A1 (en) * 1997-12-04 1999-06-09 Ford Global Technologies, Inc. Reinforced solder joints for printed circuit boards

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0921716A1 (en) * 1997-12-04 1999-06-09 Ford Global Technologies, Inc. Reinforced solder joints for printed circuit boards

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