JPS5911446A - Multiplier - Google Patents

Abstract

PURPOSE:To speed up the operating speed without requiring a complicated timing generator by constituting a multiplier with an adder and an ROM. CONSTITUTION:Binary numbers of n-bit, x, y are set to an X register 6 and a Y register 7 of a multiplier, and the content of the registers 6, 7 is added by the 1st full adder 8 of (n+1) bits. The square of the content of the registers 6, 7 and the full adder 8, X<2>, y<2>, and (x+y)<2> are obtained by ROMs 9-11 for reading out them. Further, the content of the ROMs 9, 10 is added by the 2nd full adder 12 and a product xy is obtained based on the content of the ROM11 and the adder 12 at an (n+1)-bit subtractor 13. Then, the multiplier is constituted with the full adder, the ROM and the subtractor, allowing to speed up the operating processing without providing a complicated timing generator.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a guidital multiplier for a computer or the like.

Conventionally, there has been a device of this type as shown in FIG. In FIG. 1, (1, 1s (2) shows an n-bit register, (2) a U2n-bit full adder, (4) a U2n pinpoint register, and (6) a shift timing generator, which has the above configuration. A case will be described below in which a conventional multiplier calculates the product Zi of two n-bit numbers π and y.

First, clear all the contents of registers (i) e (2) e (4) and set π to register (1) and vv to register (2).
i-Set.

Next, if the rightmost focus of register (2) is 1, the contents of register (4) and the contents of register (1) are added to full adder (8).
) and the result? Store in register (4), and shift the contents of register (4) one bit to the right. If the rightmost focus of register (2) is 0, the full adder (8
), only the contents of register (4) are shifted one pinpoint to the right.

Next, move the contents of register (2) 1 point to the right and repeat the operation sound described above. Repeat this operation n times, and then the data of ZXll is created in register (4). Multiplication is complete.

However, since conventional multipliers calculate the product using the method described above, it is necessary to perform the same procedure n times (shift and addition) to obtain the product of the number of bits The drawback is that it takes a long time.

Therefore, the present invention has been devised to eliminate the above-mentioned one drawback of the conventional technology, and it does not require a complicated circuit. A multiplier that can obtain multiplication results in a short time without the need for it, basically at the maximum speed of the constituent elements? is intended to provide.

Hereinafter, five embodiments of the present invention will be explained with reference to FIG. According to Figure 2, (6) l <7) is an n-bit binary number x
, a first full adder consisting of an n+1 pinto which adds up the contents of the X register (6) and the X register (γ); 9) s and ol) are the square values Z of the contents of the registers (6) and (γ) and the full adder (8), respectively.
"*u"*(z+y)"eThe desired read-only memory (
(hereinafter referred to as ROM), (2) a second full adder that adds the contents of ROM (9) and the second full adder, (1B) calculates the product Xν based on the contents of ROMαη and the full adder (n+1 In the illustrated configuration, when calculating the product of an n-bit number 2.v, calculation can be easily performed by applying all of the following equations.

zy=((z+y)"-(z'+11"))/2 That is, in FIG. 2, first register (6).

When setting X and ν in (γ), s ROM (
9) Data is written in (11) so that the square value corresponding to the address is output, and the mXtY register (6) * x and v, which are set to <γ, are adders. The value of the sum of 9 and its square (x + y) in (8)
” is output from the ROMα sword, and the ROM (9)
Crafted vehicle and adder (crafted on 121 (c2 + y2)
The required process will be completed. Then, 2zv is obtained by subtracting these two results and the subtractor (lal), and as a result, the product of 2+y is obtained by substituting one digit below the decimal point. That is.

In the illustrated configuration, the product xv can be determined without the need for all the conventional unsophisticated timing generators.

Well, the multiplication can be done quickly, essentially at the maximum speed of the components.

As described above, according to the present invention, since the entire multiplier is composed of an adder and a ROMK, a complicated timing generator is not required, and the calculation speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional multiplier, and FIG. 2 is a block diagram showing the entire multiplier according to an embodiment of the present invention. (6)? (7) :Register (8) $11
2): Full adder (9), shout, (1η:ROMQB):
Subtractor Agent Shin Kuzuno −

Claims (1)

[Claims] In a multiplier that calculates the product Zf of n-bit binary numbers z and v, a first full adder that adds the contents of the X register and the X register set by the n-bit binary numbers x and y, respectively; The square of each value of the register and the X register and the first full adder 'C2+uQs(z+y)'k, each read-only memory to be obtained, each squared value of an n-bit binary number x'
*The above is based on the second full adder that adds v''k, and the added value x3+2 by the second full adder and the square value (z+y) of the added value of χ and V obtained from the read-only memory. A multiplier comprising a subtractor for obtaining a product Zf of n-bit binary numbers x and v.