JPS59111374A - Pressure sensor - Google Patents

Pressure sensor

Info

Publication number
JPS59111374A
JPS59111374A JP22025782A JP22025782A JPS59111374A JP S59111374 A JPS59111374 A JP S59111374A JP 22025782 A JP22025782 A JP 22025782A JP 22025782 A JP22025782 A JP 22025782A JP S59111374 A JPS59111374 A JP S59111374A
Authority
JP
Japan
Prior art keywords
chip
resistor
resistance
integrated circuit
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22025782A
Other languages
Japanese (ja)
Inventor
Kazuji Yamada
一二 山田
Ryosaku Kanzawa
神沢 亮策
Hiroji Kawakami
寛児 川上
Ryoichi Kobayashi
良一 小林
Kaoru Shimizu
薫 志水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22025782A priority Critical patent/JPS59111374A/en
Publication of JPS59111374A publication Critical patent/JPS59111374A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/84Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure

Abstract

PURPOSE:To obtain the titled pressure sensor having little effect of residual distortion by a method wherein the cutting-out direction of a chip is selected in the direction having the smallest coefficient of piezoelectric resistance effect, and a diffused resistance is placed in parallel with the chip side, thereby enabling to suppress the effect of distortion without reducing the degree of integration. CONSTITUTION:When a chip 1 has a face <100>, its cut-out direction is set in the direction <100>. Both of the longitudinal and lateral piezoelectric resistance coefficient pil curved line 15 and pit curved line 16 in the face <100> are formed at the smallest value in the direction of <100>. If the resistor 12 for integrated circuit is arranged in the direction <100>, almost no change in resistance is generated even when the stress in parallel and orthogonal intersecting directions worked on the resistor 12. Pressure detecting resistors 3-6 are arranged in the direction where the largest piezoelectric resistance coefficient is obtained. The surface <100> has the direction in 45 deg. for the chip side.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は圧力センサに関し、特に集積化された圧力セン
サに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to pressure sensors, and more particularly to integrated pressure sensors.

〔従来技術〕[Prior art]

集積回路技術を応用した圧力センサの従来例を第1図に
示す。(a)はチップ上面図で、(b)は中央断面図で
ある。
FIG. 1 shows a conventional example of a pressure sensor using integrated circuit technology. (a) is a top view of the chip, and (b) is a central sectional view.

1は圧力センサチップで面は(100)でチップの辺は
それぞれ<110>方向に平行である。
1 is a pressure sensor chip whose surface is (100) and each side of the chip is parallel to the <110> direction.

2は裏面が、けずりとられ薄くなったダイアフラムで1
1)圧力を受けたわむ部分である。ダイアフラム部にひ
ずみ又は圧力検出用拡散抵抗3〜6が形成されている。
2 is a diaphragm with the back side cut out and made thinner.
1) It is a part that bends under pressure. Diffusion resistors 3 to 6 for detecting strain or pressure are formed in the diaphragm portion.

拡散抵抗接続部又は引き出し部7〜10が形成され、ひ
ずみ又は圧力の検出を直接的目的としない部分である。
Diffused resistance connections or lead-out portions 7 to 10 are formed and are not directly intended for detecting strain or pressure.

ダイアフラム2以外のチップ部11は固定部で、チップ
を他の支持体に固定する部分である。一般に固定部11
の表面に集積回路技術を用いて、抵抗3〜6から得られ
る信号を処理する回路が形成される。回路で用いられる
抵抗を代表して12に示した。又、トランジスタを代表
して13で示した。一般に抵抗とかトランジスタは複雑
なAt配線で結ばれているが、本願ではそれらを省略し
て図には書き表わされていない。
The chip part 11 other than the diaphragm 2 is a fixed part, which is a part that fixes the chip to another support body. Generally fixed part 11
A circuit for processing the signals obtained from the resistors 3 to 6 is formed using integrated circuit technology on the surface of the resistor. 12 shows a representative resistance used in the circuit. Further, 13 represents a transistor. Generally, resistors and transistors are connected by complicated At wiring, but in this application, these are omitted and are not shown in the drawings.

一般にレイアウト及びレイアウトのための機器の都合上
チップ辺に対して平行に抵抗を配置するレイアウトがと
られている。このレイアウト方式であると次に示すよう
に、残留応力変化に対して抵抗が変化しやすい欠点があ
る。そこでまず、p形シリコンのピエゾ抵抗効果につい
て若干の説明をする。
Generally, for reasons of layout and equipment, a layout is adopted in which resistors are arranged parallel to the sides of the chip. This layout method has the disadvantage that the resistance tends to change due to changes in residual stress, as described below. First, some explanation will be given about the piezoresistance effect of p-type silicon.

第2図において、拡散抵抗層14に電流iが流れている
とき、その長手方向に応力T5、直交方向に応力Tsが
作用すると拡散抵抗層の抵抗Rは次式で示される。
In FIG. 2, when a current i is flowing through the diffused resistance layer 14, a stress T5 is applied in the longitudinal direction and a stress Ts is applied in the perpendicular direction, and the resistance R of the diffused resistance layer is expressed by the following equation.

ここでπ1.π1はそれぞれ縦及び横ピエゾ抵抗係数で
ある。それらの係数は異方性を示し、(ioo)面の場
合、第3図に示す相対的な異方特性を示す。曲線15及
び16がそれぞれπ1及びπtを示す。第1図に示した
例では、抵抗の長手方向が(110)に平行なため、π
4及びπを共に最大値を示し、残留応力に変化が生ずる
と最も抵抗変化が生じやすい。もちろん圧力検出抵抗で
おる3〜6は<110>方向に配置することが有効であ
る。このように、一般の集積回路用抵抗と圧力検出用抵
抗では配置方向を異なるようにしなければならない。同
一方向にすると残留応力の温度変化に伴う抵抗値変化を
受は易い欠点がある。
Here π1. π1 are the longitudinal and transverse piezoresistance coefficients, respectively. These coefficients exhibit anisotropy, and in the case of the (ioo) plane, they exhibit relative anisotropic properties as shown in FIG. Curves 15 and 16 indicate π1 and πt, respectively. In the example shown in Figure 1, the longitudinal direction of the resistor is parallel to (110), so π
Both 4 and π show maximum values, and resistance changes are most likely to occur when residual stress changes. Of course, it is effective to arrange pressure detection resistors 3 to 6 in the <110> direction. In this way, the general integrated circuit resistor and the pressure detection resistor must be arranged in different directions. If they are arranged in the same direction, there is a drawback that the residual stress is susceptible to changes in resistance value due to changes in temperature.

〔発明の目的〕[Purpose of the invention]

本発明は、一般の集積回路並びに集積回路技術とピエゾ
抵抗効果を応用した圧力又はひずみセンサにおいて、信
号処理回路等、ひずみに影響を受けない抵抗をチップの
辺に平行に配置する圧力センサを提供するにある。
The present invention provides a pressure sensor in which a resistor that is not affected by strain, such as a signal processing circuit, is arranged parallel to the side of a chip in a general integrated circuit and a pressure or strain sensor that applies integrated circuit technology and piezoresistive effect. There is something to do.

〔発明の概要〕[Summary of the invention]

本発明は、一般の集積回路に用いる抵抗が、主にp形で
あることに着目し、チップの切り出し方向を、ピエゾ抵
抗効果の係数が最小な方向に選ぶことによりp形拡散抵
抗をチップ辺に平行においたとき、ひずみの影響を最も
受けにくくなることを利用したものである。
The present invention focuses on the fact that the resistors used in general integrated circuits are mainly p-type, and by selecting the direction in which the chip is cut out in the direction in which the coefficient of the piezoresistance effect is minimum, the p-type diffused resistor is placed on the side of the chip. This takes advantage of the fact that when placed parallel to , it is least susceptible to strain.

〔発明の実施例〕[Embodiments of the invention]

本発明の実施例を第4図に示す。これは、チップ(又は
ウェハ)面が(100)の場合である。
An embodiment of the invention is shown in FIG. This is the case when the chip (or wafer) plane is (100).

各部の記号は第1図と同一記号を用いたので説明は省略
する。このとき、チップの切出し方向を(100)する
ことが、集積回路の残留ひずみ影響を最小にするための
必要不可欠な条件となる。
Since the same symbols as in FIG. 1 are used for each part, explanations thereof will be omitted. At this time, cutting the chip in the (100) direction is an essential condition for minimizing the influence of residual strain on the integrated circuit.

すなわち、第3図に示したように、(100)面におけ
るピエゾ抵抗係数は、<100>方向でπj (曲線1
5)及びπt (曲線16)共に最小となる。これは、
極めて好都合である。なぜならば、抵抗を<100>方
向に配置すれば抵抗に対して、平行及び直交方向応力が
作用したとしても、はとんど抵抗変化が生じないからで
ある。一方、集積回路において、きめられたチップサイ
ズの中で集積を上げるには、できる限シ拡散抵抗を使わ
ないことであるけれども、バイポーラリニア回路では、
抵抗敷写にすることは不可能に近い技術である。そこで
、拡散抵抗配置の集積度を上げる必要がある。抵抗をチ
ップの辺に平行に配置することが効果的でおる。従って
、(10o)結晶面を使用するとき、チップ切シ出し方
向は(100)することが不可欠となる。シリコンは一
般に(11o>方向に割れ易い性質をもつため現状では
チップ切シ出し方向が<110>になっている。
That is, as shown in Fig. 3, the piezoresistance coefficient in the (100) plane is πj (curve 1
5) and πt (curve 16) are both minimum. this is,
This is extremely convenient. This is because if the resistor is arranged in the <100> direction, even if stress in parallel and orthogonal directions is applied to the resistor, the resistance will hardly change. On the other hand, in integrated circuits, in order to increase integration within a fixed chip size, it is important to avoid using diffused resistors as much as possible, but in bipolar linear circuits,
It is an almost impossible technology to apply resistance. Therefore, it is necessary to increase the degree of integration of the diffused resistor arrangement. It is effective to arrange the resistors parallel to the sides of the chip. Therefore, when using the (10o) crystal plane, it is essential that the chip cutting direction be (100). Silicon generally has a property of being easily broken in the (11o> direction, so the chip cutting direction is currently set in the <110> direction.

しかし、現在では、ダイサを用いる方法等シリコンの割
れ易さ方向にとられれる必要がなくなっているため、<
100>方向切シ出しは可能な技術である。
However, at present, there is no longer a need for methods that use a dicer, etc., to reduce the tendency for silicon to break easily.
100> direction cutting is a possible technique.

しかし、第4図に示した圧力センサにおいては圧力(又
はひずみ)検出抵抗3〜6′!il−上述した<100
>方向に配置することはできない。圧力に対する抵抗変
化感度がなくなってしまうからである。従って、圧力検
出抵抗は、ピエゾ抵抗係数が最大となる方向に配置する
ことが重要で(100)而においては、チップ辺に対し
て45 の方向となる。これは、必要十分な条件であっ
て、45゜でなければならないということではなく、場
合によっては、40 でもかまわない。要するに、固定
部11に拡散した信号処理用集積回路に使う拡散抵抗と
同一方向にすることは無意味である。
However, in the pressure sensor shown in FIG. 4, pressure (or strain) detection resistors 3 to 6'! il - <100 as mentioned above
> cannot be placed in the direction. This is because resistance change sensitivity to pressure is lost. Therefore, it is important that the pressure detection resistor is placed in the direction where the piezoresistance coefficient is maximum. This is a necessary and sufficient condition, and does not necessarily mean that it has to be 45 degrees; it may be 40 degrees depending on the case. In short, it is meaningless to set the diffused resistance in the same direction as the diffused resistor used in the signal processing integrated circuit diffused in the fixed part 11.

原理的には、第1図において、拡散抵抗12を45°の
方向に配置する方法も考えられるが、集積度の点から得
策ではない。
In principle, it is conceivable to arrange the diffused resistors 12 at 45° in FIG. 1, but this is not a good idea from the point of view of the degree of integration.

第4図の場合も、第1図と同様に、固定部11上の集積
回路は複雑であるが、拡散抵抗12及びトランジスタ1
3のみをモデル的に表わした。又At配線はすべて省略
した。
In the case of FIG. 4, as in FIG. 1, the integrated circuit on the fixed part 11 is complicated, but the diffused resistor 12 and the transistor
Only 3 was expressed as a model. Also, all At wiring was omitted.

一般に第4図に示した圧力センサは、圧力検出抵抗3〜
6をホイートストンブリッジに接続し、集積回路には、
ブリッジ駆動回路、増幅器、温度補償回路類が内蔵され
ている。ダイアフラム2は、化学エツチングで通常形成
されている。
Generally, the pressure sensor shown in FIG.
6 to the Wheatstone bridge, and the integrated circuit has
Built-in bridge drive circuit, amplifier, and temperature compensation circuits. The diaphragm 2 is usually formed by chemical etching.

他の実施例を第5図に示す。これはチップ(又はクエハ
面)が(110)面の場合である。各部の記号は第1図
と同一記号を用いたので説明は省略する。このとき、チ
ップ切り出し方向を<100>及び(110)方向にし
、集積回路内拡散抵抗を<100>方向とすることが、
集積回路の残留ひずみ影響を最小にするための必要十分
な条件である。すなわち第6図に示したように、(11
0)面におけるピエゾ抵抗係数は、<100>方向でπ
−(曲線15)及びπt (曲線16)共に最小になる
。そこで、集積回路の拡散抵抗を<100>方向にレイ
アウトすることが、必要不可欠で、先に述べたように、
集積度を上げるためには、チップ−辺が<ioo>と平
行にしなければならない。
Another embodiment is shown in FIG. This is the case when the chip (or wafer plane) is a (110) plane. Since the same symbols as in FIG. 1 are used for each part, explanations thereof will be omitted. At this time, the chip cutting directions can be set in the <100> and (110) directions, and the diffused resistance in the integrated circuit can be set in the <100> direction.
This is a necessary and sufficient condition to minimize the effects of residual strain on integrated circuits. In other words, as shown in Figure 6, (11
0) plane is π in the <100> direction.
- (curve 15) and πt (curve 16) are both minimized. Therefore, it is essential to lay out the diffused resistance of the integrated circuit in the <100> direction, and as mentioned earlier,
To increase the degree of integration, the chip-side must be parallel to <ioo>.

そこで必然的に、他の一辺に(110)となる。Therefore, the other side inevitably becomes (110).

この場合には、ダイアフラム面上の圧力検出抵抗3〜6
の配置には種々の形がある。第5図に示すように、直交
方向の感度がない<110>に平行に抵抗を並べる方式
がある。これによれば、一般の集積回路中の抵抗と直交
するように配置しなければならない。
In this case, pressure detection resistors 3 to 6 on the diaphragm surface are
There are various types of arrangement. As shown in FIG. 5, there is a method in which resistors are arranged parallel to <110>, which has no sensitivity in the orthogonal direction. According to this, the resistor must be placed orthogonal to the resistor in a general integrated circuit.

πノが最大である<111>方向及びπtが最大である
<100>から45°の方向に抵抗を配置した実施例を
第7図に示す。集積回路中の抵抗チップと平行にレイア
ウトできることから、集積度を上げ、圧力検出部は抵抗
本数が少ないので、特殊な軸に配置し、感度を高くする
ことができる。
FIG. 7 shows an embodiment in which the resistors are arranged in the <111> direction where πt is maximum and in the direction 45° from <100> where πt is maximum. Since it can be laid out in parallel with the resistor chips in the integrated circuit, the degree of integration can be increased, and since the pressure detection section has a small number of resistors, it can be placed on a special axis to increase sensitivity.

今までの説明はダイアフラムのある圧力センサで行なっ
てきたが、ダイアフラムのない一般のセンサ又はicに
も適用可能でおる。
Although the explanation so far has been made with respect to a pressure sensor with a diaphragm, it is also applicable to a general sensor without a diaphragm or an IC.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、集積回路の集積度をおとすことなく、
残留ひずみの影響が少ない集積回路又はセンサを得るこ
とができる。
According to the present invention, without reducing the degree of integration of the integrated circuit,
An integrated circuit or sensor that is less affected by residual strain can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の説明図、第2図は拡散抵抗の正面図、
第3図はピエゾ抵抗係数を示す図、第4図は本発明の一
実施例の説明図、第5図は本発明の他の実施例の説明図
、第6図はピエゾ抵抗係数を示す図、第7図は本発明の
その他の実施例の説明図である。 1・・・シリコンチップ、2・・・ダイアフラム、3〜
6・°・圧力検出抵抗、7〜10・・・接続拡散層、1
1・・・固定部、12・・・集積回路抵抗、13・・・
トランジスタ、14・・・拡散抵抗層、15・・・ピエ
ゾ抵抗係数箸/IJ (a) (//l> /) 一2m −彫 そ、5B ((A) </10〉
Figure 1 is an explanatory diagram of a conventional example, Figure 2 is a front view of a diffused resistor,
Fig. 3 is a diagram showing the piezoresistance coefficient, Fig. 4 is an explanatory diagram of one embodiment of the present invention, Fig. 5 is an explanatory diagram of another embodiment of the invention, and Fig. 6 is a diagram showing the piezoresistance coefficient. , FIG. 7 is an explanatory diagram of another embodiment of the present invention. 1...Silicon chip, 2...Diaphragm, 3~
6.°・Pressure detection resistor, 7-10...Connection diffusion layer, 1
DESCRIPTION OF SYMBOLS 1... Fixed part, 12... Integrated circuit resistance, 13...
Transistor, 14... Diffused resistance layer, 15... Piezoresistance coefficient chopsticks/IJ (a) (//l> /) 12m - Carving, 5B ((A) </10>

Claims (1)

【特許請求の範囲】[Claims] 1、 同一チップ上に拡散抵抗及びトランジスタが配置
された圧力センサにおいて、前記抵抗の長手方向がチッ
プ−辺に平行でかつ、そのチップ−辺の方向が、そのチ
ップ面のピエゾ抵抗係数の最小方向と平行であり、被測
定対象の圧力を検出するための拡散抵抗の長手方向が上
記拡散抵抗と異なる方向に配置されたことを特徴とする
圧力センサ。
1. In a pressure sensor in which a diffused resistor and a transistor are arranged on the same chip, the longitudinal direction of the resistor is parallel to the chip side, and the direction of the chip side is the minimum direction of the piezoresistance coefficient of the chip surface. A pressure sensor characterized in that the longitudinal direction of the diffusion resistance for detecting the pressure of the object to be measured is arranged in a direction different from that of the diffusion resistance.
JP22025782A 1982-12-17 1982-12-17 Pressure sensor Pending JPS59111374A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22025782A JPS59111374A (en) 1982-12-17 1982-12-17 Pressure sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22025782A JPS59111374A (en) 1982-12-17 1982-12-17 Pressure sensor

Publications (1)

Publication Number Publication Date
JPS59111374A true JPS59111374A (en) 1984-06-27

Family

ID=16748344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22025782A Pending JPS59111374A (en) 1982-12-17 1982-12-17 Pressure sensor

Country Status (1)

Country Link
JP (1) JPS59111374A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0236327A (en) * 1988-07-26 1990-02-06 Toyota Central Res & Dev Lab Inc Semiconductor pressure transducer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0236327A (en) * 1988-07-26 1990-02-06 Toyota Central Res & Dev Lab Inc Semiconductor pressure transducer

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