JPS59108968A - Thermal resistance measurement of semiconductor device - Google Patents

Thermal resistance measurement of semiconductor device

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Publication number
JPS59108968A
JPS59108968A JP21896482A JP21896482A JPS59108968A JP S59108968 A JPS59108968 A JP S59108968A JP 21896482 A JP21896482 A JP 21896482A JP 21896482 A JP21896482 A JP 21896482A JP S59108968 A JPS59108968 A JP S59108968A
Authority
JP
Japan
Prior art keywords
semiconductor device
gain
temperature
thermal resistance
power consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21896482A
Other languages
Japanese (ja)
Inventor
Kazuhiro Matsumoto
一宏 松本
Masahiro Hayakawa
雅博 早川
Yutaka Hirano
裕 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21896482A priority Critical patent/JPS59108968A/en
Publication of JPS59108968A publication Critical patent/JPS59108968A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a thermal resistance measurement of a semiconductor device which can be implemented even while the semiconductor device is in operation by incorporating a process of dividing a temperature rising value by a power consumption when the semiconductor device is used continuously. CONSTITUTION:At the step 1, a gain is measured by changing the channel temperature with varying of the source/drain voltage VD or the gate voltage VG of a semiconductor device to be measured to determine a gain vs temperature characteristic l. At the step 2, the gate voltage VG and a high frequency input RFIN are applied continuously with the source-drain voltage VD of an FET transistor 41 maintained at a fixed value to determine the current gain GI and the power consumption PDC. At the step 3, the source-drain voltage VD, the gate voltage VG and the high frequency input RFIN the same as at the step 2 are applied in a pulse to determine the current gain G2. At the step 4, the difference DELTAG is determined between the gains in the two cases at the step 3. At the step 5, the gain vs temperature characteristic l at the step 1 is used to determine a temperature rising value DELTAT corresponding to DELTAG at the step 4. At the step 6, a thermal resistance R is determined from DELTAT and PDC.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は半導体装置の熱抵抗を測定する方法に関する。[Detailed description of the invention] (1) Technical field of the invention The present invention relates to a method of measuring thermal resistance of a semiconductor device.

特に、半導体装置が実装された状態において実施するこ
とのできる、半導体装置の熱抵抗測定方法に関する。
In particular, the present invention relates to a method for measuring thermal resistance of a semiconductor device that can be carried out while the semiconductor device is mounted.

(2)  技術の背景 半導体装置は発熱体であるから、許容温間上昇値以内で
使用することが必要であり、これを可能にするために、
半導体装置の放熱効果すなわち熱抵抗を、特に実装状態
における熱抵抗を知ることが必要1ある。ここ↑、熱抵
抗とは、ある対象物に対し単位時間に与えられた熱量(
半導体装置においては消費電力)をもって、この熱量に
起因して発生した温度上昇値を除して得られる商と定義
される。そ[7て、この熱抵抗は半導体装置単体に対す
る値すなわち、チャンネルと/eフッケージ間値も重要
であるが、実装状態における値、丈なわち、チャンネル
とパッケージ以外の部材との間の値が特に重要〒ある。
(2) Background of the technology Since semiconductor devices are heat generating elements, it is necessary to use them within the permissible temperature rise value.
It is necessary to know the heat dissipation effect, that is, the thermal resistance, of a semiconductor device, especially the thermal resistance in the mounted state. Here ↑, thermal resistance is the amount of heat given to a certain object per unit time (
In a semiconductor device, it is defined as the quotient obtained by dividing the temperature rise value generated due to the amount of heat by the power consumption. [7]The value of this thermal resistance for a single semiconductor device, that is, the value between the channel and the /e hookage, is also important, but the value in the mounted state, that is, the value between the channel and components other than the package, is important. Especially important.

(3)  従来技術と問題点 半導体装置が実装されていない状態において、その熱抵
抗を測定する方法は、ΔVy法、ΔVB11法等数種本
等数種実装状態において実施しうる有効な方法は事実上
存在せず、かかる方法の開発が望まれていた。
(3) Prior art and problems There are several methods to measure the thermal resistance of a semiconductor device when it is not mounted, such as the ΔVy method and the ΔVB11 method. However, the development of such a method has been desired.

(4)発明の目的 本発明の目的は、この要請にこたえることにあり、半導
体装置が実装されていない状態においては勿論、それが
実装されている状態においても実施しうる、半導体装置
の熱抵抗測定方法を提供することにある。
(4) Purpose of the Invention The purpose of the present invention is to meet this demand, and to provide thermal resistance for semiconductor devices that can be implemented not only in the state where the semiconductor device is not mounted, but also in the state in which it is mounted. The objective is to provide a measurement method.

(5)  発明の構成 本発明に係る半導体装置の熱抵抗測定方法は、被測定半
導体装置の利得対温度特性を求め、又前記半導体装置が
連続的に使用される場合の温度における利得(G工)と
消費電力(Poo)とを測定し、更に前記半導体装置が
温度上昇を伴うことなく使用される場合の利得(G2)
を測定し、前記利得G2と前記利得G1との差(ΔG)
を求め、該利得の差と前記利得対温度特性から、前記半
導体装置が連続的に使用される場合の温度上昇値(△T
)を求め1、該温度上昇値(△T)を前記消費電力(P
DO)をもって除す過程を含ん↑構成される。
(5) Structure of the Invention The method for measuring thermal resistance of a semiconductor device according to the present invention determines the gain versus temperature characteristic of the semiconductor device to be measured, and also calculates the gain (G process) at a temperature when the semiconductor device is continuously used. ) and the power consumption (Poo), and also the gain (G2) when the semiconductor device is used without temperature rise.
is measured, and the difference (ΔG) between the gain G2 and the gain G1 is determined.
From the difference in gain and the gain vs. temperature characteristic, the temperature rise value (△T
) is calculated 1, and the temperature rise value (△T) is calculated as the power consumption (P
It is composed of ↑ which includes the process of dividing by DO).

本発明は、半導体装置例えばガリウム・砒素電界効果ト
ランジスタ(GaAs・FBT)、の高周波電力利得が
第1図に示すようにそのチャンネル温度の上昇にしたが
って減少し、しかもその利得対温度特性が線形であると
いう現象と、半導体装置が連続的に使用される場合の出
力対入力特性(利得)と半導体装置が温度上昇を伴うこ
となく使用される場合の出力対入力特性(利得)とは、
第2図に示すように特定の値(ΔG)だけ相違するとい
う現象とを用いたものである。更に、連続波を使用して
測定をなせば上記の連続的に使用される場合の値の測定
が可能であI)、パルス波を使用して測定をなせば上記
の温度上昇を伴うことなく使用される場合の値の測定が
可能であるという関係を利用している。第2図において
カーブa + bは入力信号がそれぞれ、連続波状入力
信号、ノソルス状入力信号の場合を示す。
The present invention provides that the high frequency power gain of a semiconductor device, such as a gallium arsenide field effect transistor (GaAs FBT), decreases as the channel temperature increases, as shown in FIG. 1, and that the gain vs. temperature characteristic is linear. What is the phenomenon that there is, the output-to-input characteristic (gain) when a semiconductor device is used continuously, and the output-to-input characteristic (gain) when a semiconductor device is used without temperature rise?
As shown in FIG. 2, this method uses the phenomenon of a difference by a specific value (ΔG). Furthermore, if measurements are made using continuous waves, it is possible to measure the above-mentioned values when used continuously, and if measurements are made using pulsed waves, the above-mentioned temperature increase is not caused. It takes advantage of the relationship that it is possible to measure the value when used. In FIG. 2, curves a + b indicate the case where the input signals are a continuous wave input signal and a nosorus input signal, respectively.

なお、半導体装置の消費電力としては、直流消費電力(
Poa)を使用してもおおむね満足すべき結果を得るこ
とができるが、正確には、消費電力は直流消費電力(P
no)に、高周波入力電力(PRyxs)を加え、高周
波出力電力(PRFOUT)を減じた価であるから、上
記の消費電力(PDo)に代えて、pno  PRIP
OUT +Pnyxuを使用すれば、結果は更に正確に
なる。
Note that the power consumption of semiconductor devices is DC power consumption (
Although generally satisfactory results can be obtained using DC power consumption (Poa), more precisely, power consumption is
pno PRIP
If OUT +Pnyxu is used, the results will be more accurate.

また、上記の温度上昇値(△T)は周囲温度を基準とし
て測定された値であるが、周囲温度を基準とするの1目
なく、チャンネル温度と周囲温度との中間の所望の値(
例えばシャーシ温度)を基準とする熱抵抗を求めること
が望ましいときは、上記の温度上昇値(△T)に代えて
、 △T  −Ts 但しTsは基準点(例えばシャーシ)の温度を使用すれ
ばよい。
In addition, the above temperature rise value (△T) is a value measured with the ambient temperature as a reference, but it is not based on the ambient temperature, but rather a desired value (△T) between the channel temperature and the ambient temperature.
For example, if it is desirable to find the thermal resistance based on the temperature of the chassis (for example, the chassis temperature), instead of the temperature rise value (△T) above, use △T - Ts. However, if Ts is the temperature at the reference point (for example, the chassis), good.

(6)発明の実施例 以下、図面を参照しつつ、本発明の一実施例に係る、半
導体装置の熱抵抗測定法について、東に説明する。被測
定半導体装置を、第4図に示す如く結線する。図におい
て、41は電界効果トランジスタであiJ 42.43
はインピーダンス整合回路であり、44.45は抵抗で
ある。電界効果トランジスタ4工のソースは接地されて
いる。また、電界効果トランジスタ41のゲートには、
これを通常の動作状態になすために、直流電圧VGが抵
抗44.45によって分圧され、ゲート電圧として印加
される。また、ソース・ドレイン間には直流電圧VDが
印加されている。高周波入力は整合回路42を介して緘
界効果トランジスタ41のゲートに与えられ、高周波出
力は電界効果トランジスタ41のドレインから整合回路
43を介して取り出される0 この沖1路を使用して電界効果トランジスタ41をON
 −OFF  させる動作の基本は、下記の通りである
0 まず、ゲート電圧■。の値をそのままにしてソース・ド
レイン間電圧VDを一定の範囲以上変化させれば、電界
効果トランジスタ41はその変化にしたがってON −
OFF する。
(6) Embodiments of the Invention Hereinafter, a method for measuring thermal resistance of a semiconductor device according to an embodiment of the present invention will be explained with reference to the drawings. The semiconductor device to be measured is connected as shown in FIG. In the figure, 41 is a field effect transistor iJ 42.43
is an impedance matching circuit, and 44.45 is a resistor. The sources of the four field effect transistors are grounded. Furthermore, at the gate of the field effect transistor 41,
In order to bring this into a normal operating state, the DC voltage VG is divided by resistors 44 and 45 and applied as a gate voltage. Further, a DC voltage VD is applied between the source and drain. The high frequency input is given to the gate of the field effect transistor 41 via the matching circuit 42, and the high frequency output is taken out from the drain of the field effect transistor 41 via the matching circuit 43. Turn on 41
The basics of the -OFF operation are as follows.0 First, the gate voltage ■. If the source-drain voltage VD is changed over a certain range while keeping the value of VD unchanged, the field effect transistor 41 turns ON according to the change.
Turn off.

又、電界効果トランジスタ41をON −OFFする信
号は第3図に示すようにゲート電圧■。をもって入力し
てもさしつかえない。すなわち、ソース・ドレイン間電
圧v、)は一定の値となし、ゲート電圧■。
Further, the signal for turning the field effect transistor 41 ON and OFF is the gate voltage ■ as shown in FIG. It is okay to enter with . That is, the source-drain voltage v,) is assumed to be a constant value, and the gate voltage is set to ■.

を変化させるもの〒ある。There are things that change.

以下、本発明の実施例に係る熱抵抗測定方法の各段階を
説明する。
Hereinafter, each step of the thermal resistance measuring method according to the embodiment of the present invention will be explained.

まず、第1段階として、被測定半纏体H=f4のソース
・ドレイン電圧VDまたはゲート電圧vGを種々に変え
ることによりチャンネル温度を棟々に変えて利得を測定
し、第1図に和尚する、利得対温度特性(線e)を求め
る。かかる利得対温度特性を求める場合、被測定半導体
装置に入力される信号はノξルス状信号あるいは連続信
号のいずれであってもよい。
First, as a first step, the gain is measured by variously changing the source-drain voltage VD or gate voltage vG of the semi-integrated body to be measured H=f4, and the channel temperature is varied in various ways, and the gain is measured as shown in FIG. Obtain the gain vs. temperature characteristic (line e). When determining such gain vs. temperature characteristics, the signal input to the semiconductor device under test may be either a ξ pulse-like signal or a continuous signal.

次に、第2段階として電界効果トランジスタ41のソー
ス・ Pレイン間電圧■。を一定の値に保ち、ゲート電
圧■。と高周波入力RFIN  とを連続的(cw)に
印加して、そのときの利得(G工)、及び消費″電力(
Poa)とを求める。かかる高周波入力(RFIN)に
対する高周波出力(RFOUT)特性は、第2図に曲線
aとして示される。
Next, as a second step, the voltage between the source and P-rain of the field effect transistor 41 is determined. Keep the gate voltage ■ at a constant value. and high frequency input RFIN are applied continuously (cw), and the gain (G) and power consumption (
Poa). The radio frequency output (RFOUT) characteristic with respect to the radio frequency input (RFIN) is shown as a curve a in FIG.

第3段階として、上記の場合と同一のソース゛ドレイン
間電圧■。、ゲート電圧V。、高周波入力RFIN  
とをパルス状(例えばパルス幅4〔μ日〕、デー−ティ
比〔ε%〕)に印加して、そのときの利得(G2)を求
める。かかる高周波入力(RFIN)に対する高周波出
力(RFOUT)特性は、第2図に曲線すとして示され
る。
As the third stage, the source-drain voltage ■ is the same as in the above case. , gate voltage V. , high frequency input RFIN
is applied in a pulsed manner (for example, pulse width 4 [μ days], duty ratio [ε%]), and the gain (G2) at that time is determined. The radio frequency output (RFOUT) characteristic with respect to the radio frequency input (RFIN) is shown as a curve in FIG.

第4段階として、上記二つの場合のオl]得の差(ΔG
)を下式よI)求める。
As the fourth step, the difference in the profit (∆G) in the above two cases is
) is calculated using the following formula.

O,−a、、−ΔG 第5段階として、第1段階において得られた利得対温度
特性を利用t、て、第4段階において求めたΔGに対応
する温度上昇値(△T)を求める。
O, -a,, -ΔG In the fifth step, the temperature increase value (ΔT) corresponding to ΔG obtained in the fourth step is determined by using the gain versus temperature characteristic obtained in the first step.

すなわち、第3図に示される如く、前記第1図に示され
た利得対温度特性を利用して、例えば25〔℃〕におけ
る利得(Ga)から、前記利得の差(ΔG)分だけ低い
利得Gb=(Ga−△G)に対応する温度Tを求める。
That is, as shown in FIG. 3, by using the gain vs. temperature characteristic shown in FIG. Find the temperature T corresponding to Gb=(Ga-ΔG).

該温度Tと前記2s(’c)との差△T(= T−25
)が、温度上昇値となる。
The difference ΔT (= T-25) between the temperature T and the 2s ('c)
) is the temperature rise value.

第6段階として、この温度上昇値(△T)と第2段階に
おいて求めた消費電力(PDO)とにより、下式を使用
して熱抵抗(R)を求める。
In the sixth step, the thermal resistance (R) is determined using the following formula from this temperature increase value (ΔT) and the power consumption (PDO) determined in the second step.

PDO なお以上の渦層において、前記第2段階と第3段階はそ
の順番を逆のものとしてもよい。
PDO Furthermore, in the above vortex layer, the order of the second stage and the third stage may be reversed.

(7)  発明の詳細 な説明せるとおり、本発明によれば、半導体装置が実装
されていない状態においては勿論、それが実装されてい
る状態においても実施しうる、半導体装置の熱抵抗測定
方法を提供することができる。
(7) As described in detail, the present invention provides a method for measuring thermal resistance of a semiconductor device that can be carried out not only when the semiconductor device is not mounted, but also when the semiconductor device is mounted. can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体装置の利得対温度特性を示すグラフであ
り、第2図は半導体装置のパルス状の高周波入力係号ど
連続、波としての高周波入力信号とに対する入・出力特
性の傾向を示すグラフである。 また第3図は本発明にかかる温度上列値を求める方法を
示す利得対温層特性グラフであり、第4図は本発明の一
実施例に係る半導体装置の熱抵抗測定方法が実施される
半導体装置の実施状態を示す回路図である。
Figure 1 is a graph showing the gain vs. temperature characteristics of a semiconductor device, and Figure 2 is a graph showing the trends in input/output characteristics of the semiconductor device for continuous and wave-like high-frequency input signals, such as pulse-like high-frequency input coefficients. It is a graph. Further, FIG. 3 is a graph of gain versus temperature layer characteristics showing a method for determining a temperature upper value according to the present invention, and FIG. 4 is a graph showing a method for measuring thermal resistance of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an implementation state of the semiconductor device.

Claims (1)

【特許請求の範囲】[Claims] 被測定半導体装置の利得対温度特性を求め、又前記半導
体装置が連続的に使用される場合の温度における利得(
G1)と消費電力(PDO)とを測定し、更に前記半導
体装置が温度上列を伴うことなく使用される場合の利得
(G2)を測定し、前記利得G2と前記利得G1との差
を求め、該利得の差と前記利得対温度特性から、前記半
導体装置が連続的にr重用される場合の温度上昇値(△
T)を求め、該温度上昇値(△T)を前記消費電力(P
DO)をもって除してなすことを特徴とする半導体装置
の熱抵抗測定方法。
The gain versus temperature characteristic of the semiconductor device under test is determined, and the gain (
G1) and power consumption (PDO), further measuring the gain (G2) when the semiconductor device is used without temperature increase, and determining the difference between the gain G2 and the gain G1. , from the gain difference and the gain vs. temperature characteristic, the temperature rise value (△
T), and the temperature rise value (△T) is calculated as the power consumption (P).
1. A method for measuring thermal resistance of a semiconductor device, characterized in that the method is divided by: DO).
JP21896482A 1982-12-14 1982-12-14 Thermal resistance measurement of semiconductor device Pending JPS59108968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21896482A JPS59108968A (en) 1982-12-14 1982-12-14 Thermal resistance measurement of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21896482A JPS59108968A (en) 1982-12-14 1982-12-14 Thermal resistance measurement of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59108968A true JPS59108968A (en) 1984-06-23

Family

ID=16728105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21896482A Pending JPS59108968A (en) 1982-12-14 1982-12-14 Thermal resistance measurement of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59108968A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102313613A (en) * 2011-08-04 2012-01-11 中国科学院微电子研究所 Device and method for measuring FET channel temperature
CN103411997A (en) * 2013-08-06 2013-11-27 中国科学院微电子研究所 Thermal resistance extraction method of SOI-MOSFET
RU2504793C1 (en) * 2012-06-26 2014-01-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" Method for determination of heat-transfer resistance for digital cmos integrated circuits
EP2746790A2 (en) 2012-12-24 2014-06-25 Akademia Morska The method and circuit for measuring own and mutual thermal resistances of a magnetic device
CN105806887A (en) * 2016-04-22 2016-07-27 全球能源互联网研究院 Measuring method and measuring jig for thermal resistance junction to case of power semiconductor device
RU2744716C1 (en) * 2020-01-27 2021-03-15 федеральное государственное бюджетное образовательное учреждение высшего образования "Ульяновский государственный технический университет" Method of determining thermal resistance of digital integral microcircuits

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102313613A (en) * 2011-08-04 2012-01-11 中国科学院微电子研究所 Device and method for measuring FET channel temperature
RU2504793C1 (en) * 2012-06-26 2014-01-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" Method for determination of heat-transfer resistance for digital cmos integrated circuits
EP2746790A2 (en) 2012-12-24 2014-06-25 Akademia Morska The method and circuit for measuring own and mutual thermal resistances of a magnetic device
CN103411997A (en) * 2013-08-06 2013-11-27 中国科学院微电子研究所 Thermal resistance extraction method of SOI-MOSFET
CN105806887A (en) * 2016-04-22 2016-07-27 全球能源互联网研究院 Measuring method and measuring jig for thermal resistance junction to case of power semiconductor device
RU2744716C1 (en) * 2020-01-27 2021-03-15 федеральное государственное бюджетное образовательное учреждение высшего образования "Ульяновский государственный технический университет" Method of determining thermal resistance of digital integral microcircuits

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