JPS59107565A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make parasitic capacitance between electrodes constant, and to expand a reading margin by forming the parallel first and second electrodes on a Si substrate through a first insulating film, applying constant voltage, forming a third electrode extending over both electrodes and the upper section of the substrate through a second insulating film and applying a changing signal. CONSTITUTION:The n type poly Si gate electrodes 3a, 3b are formed to the gate oxide film 2' on the p type Si substrate 1, and used as FETQ2, Q3 for transmission and clear. The gate oxide film 2'' is formed newly, and a poly Si layer 4 is formed selectively extending over a section between the electrodes 3a, 3b. The thin-film 2'' is removed while using a field oxide film 2, the electrodes 3a, 3b and the layer 4 as masks, and an impurity is introduced to form n<+> layers 5a, 5b and the gate electrode 4. The changing signal is applied to the electrodes 3a, 3b and constant voltage to the electrode 4. The displacement of the masks of the electrodes 3a, 3b and the electrode 4 is generated only in the overlapping sections of both, and parasitic capacitance is made constant regardless of displacement. Accordingly, when the device is applied to a dummy cell, fixed reference potential is obtained when a capacitance C2 is selected in consideration of constant parasitic capacitance, and the reading margin can be expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on MIS (Metal Insula
TOR Semiconductor) type semiconductor device.

It is composed of MIS type semiconductor device and has a T-type dynamic structure.
A circuit as shown in FIG. 3 is known as an AM (random access memory).

This circuit consists of a memory cell (7) composed of a capacitor (C7) for storing information, a MISFET (Q, ) for transmitting information, a preamplifier (6) for amplifying this stored information, and a preamplifier (6) for amplifying this stored information. (6) includes a dummy cell (81) that forms a read reference voltage.

This dummy cell (8) has a capacity (C2), a MISFET for transmission (C2), and a MISF for clearing.
ET (C2).

FIG. 4 is an operational waveform diagram of the circuit of FIG. 3. In operation, the clearing MISFE T of the dummy cell (8)
(C3) is turned off to finish removing the charge of the capacitor (C2)l\, and after that, the hood line signals (A, B) are set to high level and both the transmission MISFETs (Q, , C2) are turned on. On the one hand, the level of the digit line (D) is set to a level corresponding to high 1 or low storage information in the capacitor C5 of the memory cell, and on the other hand, the level of the digit line (D) is set to the level corresponding to the high 1 or low stored information in the capacitor C5 of the memory cell. The level is intermediate between the level and the low level (indicated by a broken line E), and the preamplifier (6) discriminates and amplifies the high or low level of the read signal on the digit line (D).

A cross-sectional view of the structure of the dummy cell (8) is shown in FIG.

Applying the power supply voltage (■DD) to the gate electrode (3),
n on the surface of the semiconductor substrate (1) via the gate insulating film (21).
By forming the type inversion layer (1'), the above capacitance (C
7). A gate electrode (4b) is then applied to the surface of the semiconductor substrate (1) between the semiconductor region (5b) connected to the ground point of the circuit and the inversion layer (1') to apply a clear control signal (H). MISFET for forming and clearing
(Q,)? A signal synchronized with the word line selection signal (
B) A groove electrode (4a) to which k is applied is formed to constitute a transmission MISFET (0, 2)&.

In this structure, an inversion layer (1') and a gate electrode (4b
), and when the potential (H) of the gate electrode (4b) transitions from the no level to the low level, due to the capacitive coupling of the parasitic capacitance lJ:(Cs), , clear level CF) changes. Assuming that the transition voltage of this gate electrode (4b) is V, the amount of change (Δ■) can be obtained by the following equation (11).

C7+C.

In addition, the semiconductor device can avoid mask misalignment during the manufacturing process, and the gate electrode (31) and the gate electrode (31) can be avoided.
4a, 4b), due to mask misalignment,
It is unavoidable that the surface area of the gate electrode (4b) facing the semiconductor substrate (1) through the gate insulating film (21) changes, and this causes variations in the value of the parasitic capacitance (C3), which increases the readout 7 standard. The problem of reducing the voltage high or low level read margin has become apparent.

The present invention is aimed at solving the above-mentioned problems.A constant voltage is applied to increase the main capacitance between the inversion layer immediately below the gate electrode and the gate electrode adjacent to the gate electrode. The present invention provides a semiconductor device that can maintain a constant value.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIGS. 1A to 1D are cross-sectional views showing a manufacturing process of an embodiment of a semiconductor device according to the present invention.

In the same figure (a), a field insulating film (21 pieces) is formed on a p-type semiconductor substrate @ (1), and an insulating film (2
) is selectively removed under pressure to form a gate insulating film (2')Q.

Then, the gate insulating film (2') is selectively formed on the polycrystalline silicon layer constituting the first layer of the pair, and semiconductor impurities are added to the gate made of the conductive polycrystalline silicon layer. Electrodes (3a, 3b) can be obtained. These gate electrodes (3a, 3b) are used to repair the gates of the transmission MISFET (C2) and the clearing MISFET (Q,), and in a later process, a capacitance (C2) is created between the gate electrodes (3a, 3b). Get the gate electrode? Therefore, the spacing between the gate electrodes (3a, 3b) is designed with this in mind.

As shown in the same figure (bl), using the field insulating film (2) and gate electrodes (3a, 3b) as a mask, the gate insulating film (2') is formed using self-alignment technology.
After selectively removing the gate electrodes (3a, 3a,
An insulating film (2'') is also formed on the surface of 3b).

The same gate electrode (3a as shown in 5) is the same as the gate electrode (3a).

3b) and the gate insulating film (2″) between the gate electrodes (3a
.

The gate electrode (3a) is connected through the insulating film (2') on the surface of the
, 3b) overlapping polycrystalline silicon layer (4
) selectively formed. Then, field insulating film (2
Using 1 and the gate electrodes (3a, 3b) and (4) as masks, the thin insulating film is removed to expose the surface of the semiconductor substrate (1), and the field insulating film (2) and gate electrodes (3a, 3b) are removed. , the surface of the semiconductor substrate (1) containing an n-type semiconductor impurity as a polycrystalline silicon layer (4);
It is introduced into the polycrystalline silicon layer (4) to form a semiconductor region (5a).
, 5b) and a conductive polycrystalline silicon layer (4) to obtain a second layer of gate electrode (4).

And 7, what about the insulating film on the surface of the first layer of gate electrode? A control signal (B) is applied to the gate electrode (3a) in synchronization with the word line selection signal, and the gate electrode (3b)
K is a clear control signal (H) applied. Further, a bias voltage (VDD) for forming an inversion layer (1') is applied to the gate electrode (4).

According to this embodiment described above, the clearing MISFE
The surface area of the semiconductor substrate (11), which the gate electrode (3b) constituting T (Q,) faces via the gate insulating film (2"), is defined only by the mask formed as the first layer gate electrode, In addition, the gate insulating film (2
') The substantial gate area facing the semiconductor substrate (1) is the interval between the first layer gate electrodes (3a, 3b), in other words, the distance between the first layer gate electrodes (3a, 3b). ), and the mask misalignment that forms the first layer gate electrode and the second layer gate electrode occurs only in the area where the two gate electrodes overlap. Parasitic capacitance -:f+ as mentioned above
The value of L(C3) remains constant regardless of mask displacement.

L,, 7:- Therefore, when applied to a dummy cell of this semiconductor device, in one case, since the value of the parasitic capacitance is constant, taking this into account, the capacitance i(C,) By setting a value such as , a constant reference potential can be obtained and the read margin can be expanded.

FIG. 2 is a sectional view of a semiconductor device showing another embodiment of the invention.

In this example, the first layer of gate electrodes (3a,
31)), an inversion layer (1") is placed on the gate electrode (3b).
A bias voltage (VDD) is applied to form the gate electrode (3a), and a bias voltage (VDD) is applied to form the inversion layer (1') as the first gate electrode to obtain the capacitance <C,>. The second layer gate electrode (4b) formed between 3a and 3b) is MI S F E for clearing.
A clear control signal (H) is applied to the gate electrode constituting 'r (Q3), and the second layer gate electrode (4
a) A fco signal (B) is applied to the gate electrode constituting the Q transmission MISFET (Q,) in synchronization with the word line selection signal.

In this embodiment, the substantial gate surface area of the MISFET (Q,) is determined by the gate electrodes (3a, 3) of the first layer.
b) The gate electrode (:3a) defined by the spacing, while obtaining the capacitance (C7), forms the first layer gate electrode 1
- It is possible to obtain the same effect as when using a mask.

This invention is not limited to the above embodiments, and the gate electrode is
In addition to the conductive polycrystalline silicon layer 1. A metal electrode made of molybdenum or the like, and a metal electrode made of aluminum or the like for the second layer are conceivable.

In addition to the dummy cell, the above-mentioned parasitic capacity 1
It can be widely applied to various semiconductor devices in which (C3) is a problem.

[Brief explanation of drawings]

Figures 1 (a) to (d) are cross-sectional views of the manufacturing process of one embodiment of the present invention, Figure 2 is a structural cross-sectional view of another embodiment of the present invention, and Figure 3 is a dynamic Type 11 (A M
4 is its operating waveform diagram, and FIG. 5 is a structural sectional view of a conventional semiconductor device. 0+...Semiconductor substrate, (1', 1'')...Inversion layer,
(2)...Field insulating film, (2')...Gate insulating film, (3a. 3b) -=first layer gate electrode, (4, 4a, 4b)
)...Second layer gate electrode, (5a, 5b)...
Semiconductor region, (6)...preamplifier, (7)...nomoly cell, (8)... evening cell. Figure 1 Figure 3 Figure 4 Threshold Figure 5

Claims (1)

[Claims] J, a first insulating layer formed on the main surface of the semiconductor substrate;
first and second gate electrode layers formed in parallel on the first insulating layer at a predetermined distance apart, and a main surface of the semiconductor substrate between the J-th and second gate electrodes; and a second insulating layer formed on the surfaces of the first and second gate electrode layers, and a second insulating layer on the main surface of the semiconductor substrate between the first and second gate electrode layers. a third gate electrode layer formed extending from the second insulating layer formed on the surfaces of the first and second gate electrode layers; A semiconductor device characterized in that a changing signal is applied to the layer, and a constant voltage is applied to the third gate electrode layer.