JPS59107494A - Monitor system for sound memory fault - Google Patents

Abstract

PURPOSE:To always monitor the entire area of a sound memory regardless of the output frequency of the sound data by inverting and writing temporarily each bit of the read-out data and then collation again the read-out data with the data obtained before reading and writing. CONSTITUTION:A sound memory monitor circuit 10 transmits an address (a) delivered from an address counter 11 to a memory bus 5 and reads out the sound data d1 stored in the address (a) of the sound memory part 1 to store it in a read-out data register 12. Then the logic value of each bit constituting the data d1 is inverted by an inverting circuit 13 and then written to the same address (a). Then this address (a) is transmitted to read the sound data d2 stored in the address (a) from the memory part 1. Then the data d2 is collated with the inverted data dn1 through a comparator 14. Thus it is decided that a fault arises at the address (a) if no coincidence is obtained from the collation of data.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an audio memory failure monitoring system, and more particularly to an audio memory failure monitoring system that can reliably detect audio memory failures due to random access memory in an audio output device.

(bl) Background of the Technology In voice output devices such as voice response devices or voice generators, voice is divided into voice units such as single η or phrases, and voice data that is digitally encoded for each voice unit is stored in advance in voice memory. When a desired sentence is to be output as voice, the voice data constituting the sentence is sequentially extracted from the voice memory to create and output the sentence 011.Therefore, a problem with the voice memory is due to the voice. Since it affects the quality of the output, it is necessary to detect it as early as possible and repair it quickly. tel Conventional technology and problems Figure 1 shows a conventional voice memory failure monitoring method for this type of voice output device. FIG.

In FIG. 1, a plurality of digitally encoded audio data to which parity check codes have been added are stored in advance in an audio memory section l. The control unit 2 includes an audio data transfer circuit 6- provided corresponding to the output terminals 9-1 to 9-n.
1 to 5-n, the address of the audio data without being read from the audio memory section I is sequentially transmitted via the control lot 4. Further, the clock generation unit 3 includes each audio data transfer circuit 6-1 to 5-
In order to make it possible for n to equally access the audio memory section 1,
A clock signal is generated to use the audio memory 5 in a time-divided manner in its own time domain, and is supplied to each of the audio data transfer circuits 6-1 to 6-n.

Note that audio data monitoring circuits 7-1 to 7-n and digital-to-analog conversion circuits 8-1 to 8-n are provided corresponding to the output terminals 9-1 to 9-n. Now, when the audio data transfer circuit 6-1 receives the address of the audio data to be output from the control unit 2, the audio data transfer circuit 6-1
sends the address to the audio memory section 1 via the audio memory bus 5 in the allocated time area, reads the audio data with parity check code stored at the address,
The data is transferred to the audio data monitoring circuit 7-1. The audio data monitoring circuit 7-1 performs a parity check on the received audio data with a parity check code, and if no error is detected, transmits the data to the digital-to-analog conversion circuit 8-1. The digital/analog conversion circuit 8-1 converts the received audio data into an analog audio signal, and then outputs the signal to an output terminal 9-1.
Output from. If the audio data monitoring circuit 7-1 detects an error, it notifies the control section 2 of the detection result via the control unit 4, and converts the digitally encoded audio unit into a digital-to-analog conversion circuit 8-1. Stop output to.

As is clear from the above description, in the conventional audio memory failure monitoring system, failures in the audio memory section l are monitored by inspecting the audio data read out when the audio signal is output. Therefore, the monitoring range depends on the output frequency of audio data, and there is a risk that a failure that occurs in the storage area of audio data that is output infrequently may remain latent for any period of time, and that it must be repaired in advance before outputting audio. It was difficult to keep it that way. Furthermore, in a normal parity check, there is a possibility that any fault that degenerates to a logical value of 0 or 1 will not be detected.

(dl Object of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional voice memory failure monitoring method as described above, and to be able to constantly monitor the entire area of the voice memory regardless of the output frequency of audio data. It is about realizing.

(el) Structure of the Invention The object of the present invention is to sequentially read out audio data stored at each address of the audio memory at a predetermined period in an audio output device equipped with an audio memory constituted by a random access memory. This is achieved by inverting the logical value, once writing the inverted data to the address, reading it again, and comparing it with the data before writing to detect a fault in the audio memory.

(fl　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a voice memory fault monitoring system according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating the configuration of the voice memory monitoring circuit in FIG. 2.

Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, only audio data transfer circuits 6-1 to 6-n and digital-to-analog conversion circuits 8-1 to 8-n are provided corresponding to each output terminal 9-1 to 9-n. , the audio data monitoring circuits 7-1 to 7 in FIG.
-n has been removed.

Further, an audio memory monitoring circuit 10 is provided in common to each of the output terminals 9-1 to 9-n. Also, clock creation section 3
allocates a unique time area in which the audio memory hash 5 is used not only to each of the audio data transfer circuits 6-1 to 6-n but also to the audio memory monitoring circuit 10. In FIG. 3, the audio memory monitoring circuit IO sends the address a outputted by the address counter 11, which increments by one step for each time domain, to the audio memory hash 5 in the allocated time domain, and sends the address a of the voice memory section I to the address a. The stored audio data di is successively output and stored in the data register 12.

Furthermore, the audio memory monitoring circuit IO inverts the logical value of each bit constituting the audio unit data d1 stored in the data register 12 by an inverting circuit 13 (hereinafter referred to as inverted data dnl), and then inverts the logical value of each bit constituting the audio unit data d1 stored in the data register 12 (hereinafter referred to as inverted data dnl). Write to address a. Next, the audio memory monitoring circuit 10 again sends the same address a as the previous output from the address counter 11 to the audio memory hash 5, and reads the audio data d2 stored at the address a from the audio memory unit 1. If no fault has occurred at address a of the voice memory section l, the voice unit d2 matches the inverted data dnl of the voice unit d1 read last time, but if the address a of the voice memory section 1 has a logical value. If a fault that degenerates to O or l occurs, the fault corresponding bit of audio unit d2 will not be inverted. The audio memory monitoring circuit lO reads out the audio unit d2.
and the inverted data dnl output from the inverting circuit 13 are compared by the comparing circuit 14, and if they match, the address a of the audio memory section 1 is determined to be positive '+%, and the audio m position d2
is transferred to the inverting circuit 13 via the data register 12, and the logic value of each bit is inverted again to restore the first read audio data d1, and then the audio data d1 is transferred again to the audio memory section 1 (71-
Store at address a. If the two do not match, it is determined that a failure has occurred at address a of the voice memory section 1,
After storing the first read voice unit di and address a in the status register 15, an interrupt signal is transmitted to the control unit 2 via the control bus 4. The control unit 2 that has received the interrupt signal reads the address a and the voice unit d1 stored in the status register 15, and recognizes the details of the failure. When the failure monitoring for the address a of the audio memory unit l is completed as described above, the audio memory monitoring circuit 10 increments the address counter 11 by one step. When the time domain assigned to h11 arrives again in the audio memory monitoring circuit 10, the audio memory monitoring circuit 10 monitors the next address a of the audio memory unit 1 for failure in the same process as described above. Similarly, the audio memory monitoring circuit 10 sequentially monitors the entire area of the audio memory section l for each time area assigned to itself.

As is clear from the above description, in this embodiment G, the voice memory monitoring circuit IO is independent of the voice data extraction of the voice data transfer circuits 6-1 to 5-n, and the voice memory unit 1
The entire area is sequentially monitored at a predetermined period. However, it is possible to detect any fault that occurs, even if it degenerates to either logical value O or l.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and the configuration of the audio memory monitoring circuit 10, for example, is not limited to that illustrated, and many other modifications may be considered. However, the effects of the present invention do not change in either case.

Further, the configuration of the audio output device to which the present invention is applied is not limited to that shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case.

(gl) Effects of the Invention According to the present invention, in the audio output device, the entire area of the audio memory is constantly and equally monitored regardless of the output frequency of audio data, and the output audio can be maintained at high quality. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional audio memory fault monitoring system, FIG. 2 is a diagram showing an audio memory fault monitoring system according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the audio memory monitoring circuit in FIG. 2. It is a figure which illustrates a structure. In the figure, ■ is an audio memory unit, 2 is a control unit, 3 is a clock generation unit, 4 is a control unit, 5 is an audio memory unit, 6-
1 to 6-n are audio data transfer circuits, 7-1 to 7-n
is an audio data monitoring circuit, 8-1 to 3-n are digital/analog conversion circuits, and 9-1 to 9-n are output caps 1 (,
1 child, IO is an audio memory monitoring circuit, 11 is an address counter, 12 is a data register, 13 is an inversion circuit, 14 is a comparison circuit, 15 is a status register, 16 is a timing control circuit, a is an address, dl and d2 are audio Data and dnl indicate inverted data. 1st fd 2nd Q

Claims (1)

[Claims] In an audio output device equipped with an audio memory constituted by a random access memory, the audio data stored in each address of the audio memory is sequentially read out at a predetermined period, the logical value of each constituent bit is inverted, and after the inversion, 1. An audio memory failure monitoring method, wherein a failure in the audio memory is detected by once writing data to the address, reading it again, and comparing it with the data before writing.