JPS59106899A - Control device for motor - Google Patents

Abstract

PURPOSE:To exponentially drive in a simple structure by providing a IIR digital filter and an integrating resistor. CONSTITUTION:When a power surce becomes ON, a CPU initially sets a memory RAM, an I/O port and a counter. Then, a port connected to a drive direction instruction input CW/CCW of a motor drive circuit MD is set to CW level, and a target speed data corresponding to the speed IV is set to the output port connected to the primary IIR digital filter FLT. Since the IIR digital filter responds to the exponential function of K.DELTAt at the time constant, the exponential output can be obtained by merely applying the prescribed stational signal to the input. Accordingly, a step motor 4 is automatically accelerated in accordance with an exponential curve.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a control device that generates pulses corresponding to a driving amount to drive a stepping motor, a DC servo motor, etc., and particularly relates to acceleration/deceleration control of a motor.

■Prior Art When driving a stepping motor or a DC servo motor equipped with a rotary encoder that generates a signal according to rotation, pulses are generated according to the amount of motor drive to displace the motor by a predetermined amount.

Incidentally, known methods of motor acceleration/deceleration control include trapezoidal wave drive, quadratic curve drive, and exponential function drive, which change the speed in a trapezoidal manner. In trapezoidal wave driving, since the acceleration during acceleration and deceleration is constant, it is relatively easy to control changes in the pulse period, etc., and this method is generally used.

However, in fields where vibration-free and smooth operation is required, such as scanning drive of a copying machine optical system, it is most preferable to use exponential function drive. However, in exponential drive, the acceleration during acceleration and deceleration is not constant, so an exponential timing signal must be generated, making control to generate drive pulses extremely difficult. Devices generally have very complicated device configurations.

As an example of exponential function driving, for example, the
-10679 is known. However, even this requires a large number of components such as read-only memory, address counter, preset counter, divider, etc.
It is inevitable that the device configuration will become complicated.

(2) Purpose of the Invention The object of the present invention is to realize a motor acceleration/deceleration control circuit that performs exponential function drive with a relatively simple configuration.

(2) Structure In order to achieve the above object, in the present invention, target speed data is input to a primary ITR digital filter, the output of this filter is integrated, and a motor drive pulse is generated every time a predetermined change in the integrated output.

In a -order TIR digital filter, the nth input is
When n and the n-th output are yn, the following equation is obtained.

yn =Σ(Xn-, &n-+)/K...
(1,)ru.

Therefore, the transfer function of this filter is expressed by the following equation.

Y(s)=X/(10K·Δts)−(2) However, Δt is the clock pulse period.

Therefore, the output change when input X is a step signal is expressed by the following equation.

y (shi) = λ (1-εσ) However, α=X/K·Δt.

In other words, the -order IIR digital filter has a time constant of K.
・Since the response is an exponential function of Δt, an exponential output can be obtained simply by applying a predetermined fixed signal to the input.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic diagram of an electric circuit of an optical system scanning device of a copying machine embodying the present invention. This will be explained with reference to FIG. 4 is a four-phase stepping motor serving as a driving source, and each excitation coil of this stepping motor is connected to a motor drive circuit MD.

A microcomputer CPU controls the motor 4. In this example, the CPU is comprised of a microprocessor unit MPU, read/write memory RAM, read-only memory ROM storing operating program data, a counter, and ■/○ ports (outputs with latches).

Connected to the input end of the I10 boat are a home position sensor, a limit switch for detecting a forward scan limit position, and an output end for a scan start instruction signal from a main controller (not shown). A drive direction instruction input terminal CW/CCV of the motor drive circuit MD is connected to one output terminal of the I10 baud 1-. A primary TIR digital filter FLT is connected to the remaining output end of the I10 port, and an integration register ITR is connected to the output end of this filter FLT. A step pulse output end (motor drive pulse output end) of the integral register is connected to a step pulse input end of the motor drive circuit MD and a counter of the CPU.

To explain the first-order IIR digital filter FLT, it consists of a first full adder B B1 . , second full adder BB2. B2-consists of a register BB3 and a complement circuit BB4. The first full adder BBI outputs the difference between the input data from the ■/○ boat and the output data of the speed register BB3 (obtained by the complement circuit BB4), and the second full adder BB2 outputs the difference between the input data from the The output data is added to the output data of the full adder BBI by 1/K (in this example, 1, /16 as described later). Speed register BB3
The output data is also output to the integral register TTR.

Speed register BB3 receives external clock pulse CL.
Input data is latched by K1.

The integral register ITR consists of a third full adder CCI and a register CC2. The full adder CCI is a filter F
The speed data from the LT and the output data of the register CC2 are added, and the register CC2 launches the output data of the full adder CCI in response to an external clock pulse CLK2.

Figure 2 shows the -order IIR digital filter FL in Figure 1.
The detailed configuration of T and integral register ①TR is shown. Second
This will be explained with reference to the figures. A, D] to AD4 are the first full adders BB], AD5 to AD8 are the second full adders BB2,
AD9 to AD]3 is the third full adder CCI. FF
I to FF4 are speed register BB3 and complement circuit F3
It is a flip-flop that constitutes B4, and FF5 to FF
9 is a flip-flop constituting the register CC2.

Full adder AD I - AD I 3 used here
is a 4-bit full adder 5N748283 made by Texas Instruments, and the flip-flops FF1 to F
F9 is the company's 4-pitch 1-D type flip-flop 5.
N74S]75. The full adders AD1 to AD]3 are
A input terminals A1 to A4, respectively. B input end B] ~B4. C input terminal CO9 addition output terminal Σ1 to Σ4 and carry output terminal c
4, the data at the A input terminal, B input terminal, and C input terminal are added and outputted to the Σ output terminal, and when the addition result overflows, a carry is output. Flip-flops FFI to FF9 have D input terminals 10, 20, and 3D.

4D, Q output terminals], Q, 2Q, 3Q, 4Q, inverted output terminals Iζ, 2◇, 3G, 4 points, and a clock pulse input terminal CK. In this embodiment, the least significant digit full adder AD
The minimum carry power CO of 4 is set to 1, and the ◇ output terminals of the flip-flops FFI to FF4 are used as the output terminal of the complement circuit BB4.

Full adder BBI consists of four 4-bit full adders ADI~A,
It has a 16-bit configuration using D4, and the input terminals of each are connected to the ■/○ ports of CPT and J.

The B input terminals of ADI to AD4 are speed registers FFI to F.
It is connected to the inverted output terminal of the corresponding digit of F4 (BB3). The output terminals (Σ) of the full adders FFI to FF4 are respectively connected to the input terminals of the full adders AD5 to AD8, which are 4 bits lower (1/16) than the corresponding digit.

Since the most significant bit Σ4 of AD1 has a sign of I-, it is also connected to all input terminals of the full adder AD5 to match the signs. The Q output terminals of speed registers FF 1 to FF 4 are connected to the B input terminals of the corresponding digits of full adders AD5 to AD8, and the output terminals (Σ) of AD5 to AD8 are connected to the FFI
- Connected to the D input terminal of the corresponding digit of FF4.

Integral register ITR consists of five 4-bit full adders AD9
~AD1.3 has a 20-bit configuration, and the output data of the filter FLT is applied to the input terminal of the lower 16 bits. The B input terminals of AD9 to AD1.3 are connected to the Q output terminals of registers (flip-flops) FF5 to FF9, and the D input terminals of FF5 to FF9 are connected to the A
, D9 to AD13 are connected to the Σ output terminals. Also, in order to match the signs, the most significant bit (MSB) is connected to all input terminals of AD9. The output end 4Q of the register FF5 is led out to the outside as a motor drive pulse (step pulse) output end. In other words, 4Q of FF5
By changing the level twice, one step pulse is output.

FIG. 3 shows details of the motor drive circuit MD and motor 4 shown in FIG. 1. This will be explained with reference to FIG.

In this embodiment, Sanyoden fJj is used in the phase excitation distribution circuit.
J, universal controller IC, PMM8713
are using. Then, pull up pins 5.6 and 7 of the PMM8713 to H to select the 1-2 phase excitation mode for the 4-phase motor. Output end Φ1. Φ2. Φ3 and Φ4 are respectively connected to power amplifier AI,
A2. A3 and A4 are connected to the power amplifier A1
The output ends (collectors) of ~A4 are connected to one end of the excitation coils 4a, 4b, 4c, and 4d of the stepping motor 4, respectively. The other ends of the excitation coils 4a to 4d are connected to each other and to the collector of the transistor Tri via a resistor R. The resistance value of the resistor R is set to 1/J7 times the DC resistance r of each exciting coil 4a to 4d. MC14538 is a monomulti IC made by Molola.
and its input terminal (pin 5) is Co of PMM8713.
(input pulse monitor), and the output end is connected to T r 1 via a 1-transistor T r 2. At the emitter end of TRL, there is a DC constant voltage + for driving the motor.
Vd is applied thereto, and a DC constant voltage ->-Vh (Vd>Vh) is applied to the collector end of Tri via the diode D1. Direction signal CW/C sent by CPU
CW becomes CW (clockwise), Ck of 2MM8713
When a step pulse is applied at the end, each excitation phase Φ1~Φ
4 sequentially becomes the excitation level (H), and accordingly transistors 1 to A4 of amplifiers A to A4 are turned on. On the other hand, when a step pulse is input, the 2MM8713 outputs a pulse signal to the Co terminal, and as a result, a pulse signal of a predetermined width appears at the output terminal of the MC]4538. The pulse signal turns on the transistors T r 2 and Trl for a predetermined period of time, and current flows through the resistor R to the excitation coils 4a to 4d connected to the one of the amplifiers A1 to A4 (7) that is turned on.

4a and 4b show schematic operation timings of the first-order TIR digital filter FLT and the integration register ITR of FIG. 2.

First, explanation will be given with reference to FIG. 4a. Full adder AD1~A
When the target speed data applied to the A input terminal of D4 is O, the value appearing at the output of the filter FLT also becomes 0. When driving the motor at a predetermined speed V, a numerical value corresponding to V is set as target speed data from the beginning.

When the target speed data is set, the filter FLT is
It changes in synchronization with the clock pulse CLKI applied to the flip-flops FF1 to FF4, and this change follows an exponential function curve with a time constant according to the period of the clock pulse CLK]. Then, the speed converges to a predetermined value corresponding to the target speed ■. That is, once the output of the filter FLT reaches the target speed, it automatically settles down to a predetermined value as time passes.

When stopping the motor, set O as the target speed data.
Sera 1-. Then, the output numerical value of the filter FLT decreases exponentially in synchronization with the clock pulse CL K ], and automatically settles to 0 after a predetermined time has elapsed.

Integral register ITR includes flip-flops FF5 to FF.
The speed data applied to the A input terminals of full adders AD9 to AD13 is integrated in synchronization with the clock pulse CLK2 applied to 9, and the result is integrated to the flip-flops FF5 to F.
Set it to the output terminal of F9. That is, for example, if the data of the output Q of the flip-flops FF5 to FF9 is 0 at first, and 5 is output from the filter FLT,
5 (500) is output to the output terminals Σ of full adders AD9 to A and D13, and this is the next tarok pulse (CLK2).
is set in flip-flops FF5 to FF9.

Next, when 7 is output from FLT, full adder AD
9-AD] 12 appears at the output terminal Σ of 3, and when the next clock pulse (CLK2) is applied here, 12 is set in the flip-flops FF5-FF9. Integration is performed in the same manner thereafter, and the flip-flops FF5 to F
The value of F9 output gradually increases. And F.F.
When the level of 4Q of No. 5 changes, that is, every time the integral value changes by a predetermined value, a motor drive pulse (step pulse) is output.

1 while the value applied to the integral register ITR is small.
The change in the integral value with respect to the clock pulse is small, so the appearance period of the motor drive pulse is long (that is, the motor rotation speed is slow), but as the output value of the filter FLT increases, the appearance period becomes shorter, and the motor accelerates. be done. When the output value of FLT converges to a constant value, the amount of change in the integral value of GoR with respect to one clock pulse also becomes constant, the motor drive pulse cycle becomes constant, and the motor enters a constant speed drive state. Stop the motor
The same applies to the case of
The period of appearance of the dynamic pulse gradually becomes smaller, and P L,
When the output value of T, that is, the Δ input of the full adders AD9 to ADI3, becomes 0, two values are no longer added, so the integral output value changes and disappears, and the drive pulse no longer turns off.

FIG. 5 shows the already +118 operation of the microcomputer CP[I of FIG. 1. This will be explained with reference to FIG.

First, when the power is turned on, the CPU uses the memory RAM,
Initialize (reset) the I10 port, counters, etc. Next, the port connected to the drive direction specifying human power CW/CCW of the data drive circuit MD is set to the CW level, and the target corresponding to the speed v1 is set to the output capo-1- connected to the primary TIR digital filter FLT. Set the speed data to 1~. Acceleration is then automatically performed according to the exponential curve, and the motor 4 performs forward scanning drive.

Wait until the counter counts a predetermined number N1 of step pulses, and when the count is finished, send data corresponding to speed 0 to port 1 connected to filter FLT. This automatically decelerates and changes the cycle of the step pulses, so it is determined whether or not the motor has stopped by looking at changes in the contents of the counter.

When the motor stops, the level of the direction specifying input terminal of the motor drive circuit MD is set to ccw at 9 degrees, and the filter F is
Set data for speed 2 in LT and start backward scanning. The output of the input position sensor is monitored to check whether the home position has been reached. When the home position is detected, data with a speed of 0 is sent to the filters FT and T and waits until the data stops.

Once the motor has stopped, wait until the main controller instructs you to start scanning. When a scan start instruction is given, set the scan direction designation side of the motor drive circuit MD to the forward direction CW, and send data corresponding to the target speed v1 to the filter FLT.
do. Now start forward scanning.

The counter finishes running 1- for the number of steps N2 from the forward scanning start position to the forward scanning end position. !
Mino 1 - When the switch is turned on, filter F L
Data corresponding to speed 0 is sent to T, and waits until the motor 4 stops.

When the motor stops, set the direction designation input of the motor drive circuit MD to the backward scanning direction CCW level, and
Data corresponding to the target speed V2 (V2>Vl,) is set in T-T. Now start backward scanning. Ho 1
1 Monitor the d4 level of the position sensor and wait for the scanning system to reach the home position.

When the scanning system reaches the home position, set zero speed data in the filter FLT and wait for the motor to stop.

Once the motor has stopped, check again to see if there is an instruction to start scanning, and repeat the above operations.

In the second embodiment, the output of the predetermined bit of the integral register ITR is directly used as the motor drive pulse output, but a circuit is provided to store the integral output data when a clock pulse is generated, and this stored value and the integral output data are combined. The next step pulse may be generated when the difference between the two reaches a predetermined value.

In addition, although no special explanation is given regarding the clock pulse CLK1 applied to the filter FLT and the clock pulse CLK2 applied to the integration register ITR in the embodiment, a frequency divider capable of changing the frequency division ratio is provided for the output of the oscillator. The period of CL K 1 and/or CI-K 2 may be changed in accordance with the target speed of the motor, thereby changing the time constant of the exponential function curve.

Furthermore, although the embodiment describes the case of driving a stepping motor, the present invention can be applied to a control device that connects a rotary encoder or the like to a DC servo motor and generates drive pulses according to the detected motor position. can be carried out.

In the embodiment, the outputs of the first full adders ADI to AD4 are ], / ] 6 L, and the outputs of the second full adders AD
5 to AD8 is applied, but this coefficient (I<) can be arbitrarily determined. However, in order to simplify the configuration, set K to 2.
It is preferable that the number is one note.

(■Effects As described above, according to the present invention, there is no need to store a large number of speed data in memory, and moreover, by resetting one speed data once, the speed is automatically controlled in an exponential manner.) Therefore, the control is simple q1 and the device configuration is 111.
Become pure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an electric circuit of an optical system scanning device of a copying machine embodying the present invention. FIG. 2 shows the first-order TIR digital filter F shown in FIG.
FIG. 2 is a block diagram showing a detailed configuration of L, T and an integral register ITR. FIG. 3 is a block diagram showing the motor drive circuit MD of FIG. 1 in detail. FIGS. 4a and 4b are timing charts showing the general operation of the -order IIR digital filter FLT and the general operation of the integration register TTR, respectively. FIG. 5 is a flowchart 1- showing a schematic operation of the microcomputer CPU of FIG. 4 chipping motor CPU: Microcomputer (target speed output means)
FLT knee-order ■IR digital filter TTR: Integral register (integrator circuit) MD: Motor driver ADI to AD13: 4-bit full adder FFI to FF9: 4-bit I-D flip-flop A
1-A4: Power amplifier

Claims (1)

[Claims] Target speed output means for holding target speed data consisting of a combination of binary information; -th TIR connected to the output of the target speed output means;
a digital filter; an integrating circuit that integrates the output information of the -order IIR digital filter and outputs a motor driving pulse every predetermined change in the integrated output; and a motor driver that drives the motor in accordance with the output pulse of the integrating circuit; A motor control device comprising: