JPS59106141A - Suppression of electromagnetic wave noise in semiconductor integrated circuit - Google Patents
Suppression of electromagnetic wave noise in semiconductor integrated circuitInfo
- Publication number
- JPS59106141A JPS59106141A JP57217165A JP21716582A JPS59106141A JP S59106141 A JPS59106141 A JP S59106141A JP 57217165 A JP57217165 A JP 57217165A JP 21716582 A JP21716582 A JP 21716582A JP S59106141 A JPS59106141 A JP S59106141A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package
- electromagnetic wave
- power supply
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49589—Capacitor integral with or on the leadframe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【発明の詳細な説明】
本発明は、半導体集積回路（ｒｃ）における雑音電磁波
の抑制方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for suppressing noise electromagnetic waves in a semiconductor integrated circuit (RC).
近年、マイクロコンピュータ等、ディジタルＩＣを使用
した各種ティンタル電子機器の普及に伴って、これらの
機器から発生する雑音電磁波による他の電子機器への妨
害が問題となっている。ディジタル電子機器か雑音電磁
波を発生する主たる原因は、ディジタル回路の主要構成
部品であるディジタルＩＣが動作する際、魚鱗な電圧、
電流の変化が発生するために、高周波成分を含む電流が
、機器の電源やグランドラインに流れろことによる。In recent years, with the spread of various electronic devices using digital ICs, such as microcomputers, interference with other electronic devices due to noise electromagnetic waves generated from these devices has become a problem. The main cause of noise electromagnetic waves generated by digital electronic devices is when digital ICs, which are the main components of digital circuits, operate,
This is due to the fact that current containing high-frequency components flows through the equipment's power supply and ground line due to the change in current.
電源ライン等に流れた高周波電流は、電源ラインのパタ
ーン等をアンテナとして電磁波となって、機器内外へ放
射される。機器内へ放射された電磁波は、機器外へ接続
された配線を受信アンテナとして、再度ラインに流入し
、これか機器外へ漏洩し、他の電子機器に影響を与える
こととなる。High-frequency current flowing through a power line or the like becomes an electromagnetic wave using the pattern of the power line as an antenna, and is radiated into and out of the device. The electromagnetic waves radiated into the device enter the line again using the wiring connected to the outside of the device as a receiving antenna, and then leak out of the device and affect other electronic devices.
従来、電子機器から発生する妨害電磁波を防ぐ手法とし
て、電子機器から発生する電磁波を機器外に出さないよ
うに機器の筺体をシールド構造にしたり、外部と接続さ
れる配線に、フィルターを挿入したりしていた。しかし
ながら、これらの手法によるものは、高価であったり、
実施効果か期待したほど挙げられないなどの欠点があっ
た。Traditionally, methods for preventing interference from electromagnetic waves generated by electronic devices include creating a shield structure for the casing of the device to prevent the electromagnetic waves generated from the device from escaping the device, and inserting filters into the wiring connected to the outside. Was. However, these methods are expensive and
There were some shortcomings, such as the effects of implementation not being as high as expected.
それ故に、これまで、ディジタルＩＣの発生する雑音電
位波自身を抑制する手法がいくつか提案されている。Therefore, several methods have been proposed to suppress the noise potential waves themselves generated by digital ICs.
第１図は、従来のこの種の手法の一例を示す説明図であ
る。この手法は、ディジタルＩＣ１の電諒ライソバター
ン２と、延１＋：さねたグランドパターン６どの間にコ
ンデンサ４を仲々接続（７たものである。この手法は、
ディジタル■ＣＬ１）Φυ作に」−る市１流の変化・２
、コンデンサ−４の充放電特性（てより緩和１〜、かつ
１Ｌ源やグランドライン゛１マ！′ン・、電磁波の放射
アンプ′すとして動作し１ｃいように、コンデンサ４か
高周波的にショートイ−イ）もので、ｂる。FIG. 1 is an explanatory diagram showing an example of a conventional method of this type. In this method, capacitors 4 are connected between the conductor pattern 2 of the digital IC 1 and the grooved ground pattern 6 of the digital IC 1.
Digital ■CL1) Φυ's first-rate changes in the city 2
, the charging and discharging characteristics of the capacitor 4 (more relaxed 1~, and the capacitor 4 should be short-circuited at high frequency so that it operates as a 1L source or ground line amplifier), and operates as an electromagnetic wave radiation amplifier. i-i) It's something.
しか１−ながら、このよう７ｒ手法によっても、なお、
第１図において斜線を施（また部分５か、雑ｔ”ｉ＝電
磁波放射ループを形成し、雑音電磁波を効果に抑制する
ことはできなかった。１時に、高集積ハｌ ｏ−＞ Ｉ
Ｃである場合、ＩＣの消費電流か増加するとともに人
出力ピン数か増加し、この結果、電源ラインパターンと
グランドパターンとの距離か離れたり、リードフレーム
の長さ等によって、雑音１Ｌ伝党波に対して長いアンテ
ナを提供することとなり、雑音電磁波の放射を完全に抑
制することは困難でｋ）つた。However, even with this 7r method,
In Fig. 1, the diagonal line (also part 5) forms an electromagnetic wave radiation loop, making it impossible to effectively suppress noise electromagnetic waves.
In the case of C, the number of output pins increases as the current consumption of the IC increases, and as a result, the noise 1L propagation wave increases depending on the distance between the power line pattern and the ground pattern, the length of the lead frame, etc. Therefore, it was difficult to completely suppress the radiation of noise electromagnetic waves.
ここにおいて、本発明は、高集積度のＩＣに対しても効
果的に雑音電磁波の放射を抑制できる手１／２：？′１
２胡↓（シ、）、５と−Ｊ−イ）ものであ４）。Here, the present invention can effectively suppress the emission of noise electromagnetic waves even for highly integrated ICs. '1
2hu↓(shi,), 5 and -J-i) mono de 4).
本発明に保イ）手法は、Ｉ Ｃ−チップの′屯丼ピンと
グランドビン間にバイパス−Ｉンーｊンヅを′接続し７
、このバイパスコンデンサなＩＣパノク−−ジ内（Ｃ封
入さ七、利−音電磁波ケＩＣ−：ソクーーージ内ｉｃお
いて抑ｊｌｉｌｌ−Ｊ−イ・ようにしｌこものでｋ）４
）。The method retained in the present invention is to connect a bypass pin between the pin of the IC chip and the ground pin.
, This bypass capacitor is inside the IC pano cage (C enclosed, sonic electromagnetic wave IC: suppressed in the internal IC) 4
).
第２図は１本発明の手法の一例を説明４′イ）ための説
明図でル）ろ。この図にｔｄいて、１ばＩＣバッタージ
、１０はこのパノク−一−−ジ内に設に１−されてぃ７
：、）Ｉ Ｃナツプ、１１ばこのＩＣチップから出てぃ
イ）′市諒ビン、１２はＩＣチ７ンブか１出ているグラ
ンドビンで、こハ、［）のビンは、そＪしそれ電源リー
ドパターン２０．グランドリードパターン６ｏを介して
、パッケージ１の外部に出てぃイ）端子２１゜３１に接
続され℃い４）。４（」本発明において特徴としている
バイパスコンデンサで、ＩＣナツプ１゜の電υリミビン
１１と、グランドビン１２との間に接続されている。ま
た、このバイパスコンデンサ４ば、ＩＣパッケージ１内
に、ｔ Ｃチップ１ｏとともに封入される。FIG. 2 is an explanatory diagram for explaining an example of the method of the present invention. In this figure, 1 is the IC battage, and 10 is the IC battery installed in this panochage.
:,) I C nap, 11 is coming out of the IC chip) 'Ichiyo bin, 12 is the grand bin with IC chip 7 or 1 coming out, and the bottle in [) is that J. It's power lead pattern 20. It exits from the package 1 via the ground lead pattern 6o and is connected to the terminals 21 and 31 (4). 4(') is a bypass capacitor that is featured in the present invention, and is connected between the voltage limit bin 11 and the ground bin 12 of the IC nap 1°. It is enclosed together with the tC chip 1o.
このように構成されろ素子によれば、／・イハスコンデ
ンサ４が、ＩＣチップ１０から出ているビンに接続され
、しかもＩＣパンケージ内に封入されていることから、
ＩＣチップ１内で発生した雑音電磁波は、放射アンテナ
となり得るリードパターンや配線に到達する以前にショ
ートされ２）。また、コンデンサの充放電特性の妨げと
なる分布抵抗値やインダクタンスを極めて低い値に押え
４・ことができる。According to the element configured in this way, the IHAS capacitor 4 is connected to the bottle protruding from the IC chip 10, and is furthermore enclosed within the IC pancase.
The electromagnetic noise generated within the IC chip 1 is short-circuited before reaching the lead pattern or wiring that can serve as a radiation antenna 2). Further, the distributed resistance value and inductance, which impede the charge/discharge characteristics of the capacitor, can be kept to extremely low values 4.
したがって、本発明に係る手法によれば、雑音電磁波の
放射な高密度化（〜たｔＣであっても効果的抑制するこ
とができる。また、外来の雑音電磁波に対しても、外部
に対する高周波的な結合か弱くできるので、誤動作する
ことを防止できろ。Therefore, according to the method according to the present invention, it is possible to effectively suppress even high-density emissions of noise electromagnetic waves (~tC).Also, with respect to external noise electromagnetic waves, high-frequency radiation to the outside can be effectively suppressed. Since the connections can be weakened, malfunctions can be prevented.
木兄虹に係る手法は、ディジタルＩＣ以外のアナログ信
号を扱うアナログＩＣに適用してもイｊ効である。The technique related to Kienji is also effective when applied to analog ICs that handle analog signals other than digital ICs.
第１図は従来の手法の一例を示す説明図、第２図は本発
明の詳細な説明するための説明図である。
１・ Ｉ ｃパッケージ １０・・ＩＣチップ１１・・
・１トｄ９ビン １２・・グランドビン４・・・
バイパスコンデンサ
代理人 葛 野 情 −FIG. 1 is an explanatory diagram showing an example of a conventional method, and FIG. 2 is an explanatory diagram for explaining the present invention in detail. 1. Ic package 10... IC chip 11...
・1t d9 bin 12...Grand bin 4...
Bypass capacitor representative Jo Kuzuno −
Claims (1)
イパスコンデンサな一接続し、このバイパスコンデンサ
を前り己ＩＣチップとともにＩＣパッケージ内に封入さ
せ、雑音電磁波をＩＣパッケージ内において抑制するよ
うにしたことを特徴とする半導体集積回路における雑音
電磁波の抑制方法。(1) A bypass capacitor is connected between the power supply pin and the ground pin of the IC chip, and this bypass capacitor is sealed in the IC package together with the IC chip to suppress noise electromagnetic waves within the IC package. A method for suppressing noise electromagnetic waves in a semiconductor integrated circuit, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57217165A JPS59106141A (en) | 1982-12-10 | 1982-12-10 | Suppression of electromagnetic wave noise in semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57217165A JPS59106141A (en) | 1982-12-10 | 1982-12-10 | Suppression of electromagnetic wave noise in semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59106141A true JPS59106141A (en) | 1984-06-19 |
Family
ID=16699872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57217165A Pending JPS59106141A (en) | 1982-12-10 | 1982-12-10 | Suppression of electromagnetic wave noise in semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59106141A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6245848U (en) * | 1985-09-06 | 1987-03-19 | ||
| CN107181056A (en) * | 2017-05-16 | 2017-09-19 | 叶云裳 | A kind of microwave attenuation type high stable phase, high-precision GNSS measurement type antenna and equipment |
-
1982
- 1982-12-10 JP JP57217165A patent/JPS59106141A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6245848U (en) * | 1985-09-06 | 1987-03-19 | ||
| CN107181056A (en) * | 2017-05-16 | 2017-09-19 | 叶云裳 | A kind of microwave attenuation type high stable phase, high-precision GNSS measurement type antenna and equipment |
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