JPS59104144A - Forming method for salient electrode - Google Patents

Abstract

PURPOSE:To stably control the etching of a deposited layer by performing a heat treatment to accelerate the alloying of the layer and a salient electrode material before etching and removing a common electrode. CONSTITUTION:After an Au plating layer 5 is formed a heat treatment is performed before etching a deposited layer 4. An Ag-Au diffused layer is formed between Ag and Au plating layers 5 for forming a buffer layer 4b by this heat treatment. Since the Ag-Au diffused layer has much slower etching speed than the etching speed of Ag to etchant of the layer 4b, the lower part of the layer 5 formed with the Ag-Au diffused layer has a wide etching time margin to the side etching with the etchant of the layer 4b and can be sufficiently allowed for the irregularity in the thickness of the layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming protruding electrodes (bumps) of an IC.

In recent years, in order to achieve thin, compact, and low-cost packaging, finger electrodes are formed at the same time as the circuit pattern is formed.
TAB (Tape Automated B
ondiug) The mounting method is widely adopted.

A conventional bump forming method will be explained below with reference to FIG.

FIG. 1 is an explanatory diagram showing a bump structure in the prior art and the present invention, in which 1 indicates an Al pad for an IC 12, and 6 indicates a passivation film. 4 indicates a vapor deposition layer, and the vapor deposition layer 4 is formed by applying CT as an adhesive layer 4a of the first vapor deposition layer to the entire surface of the wafer using a film forming method such as a resistance heating vapor deposition method.
The buffer layer 4b of the second vapor deposition layer is made of Ag to a thickness of about 200A to 10,000A. After forming the vapor deposited layer 4, the Menki resist is opened only in the area corresponding to the A-e pad 2 so as to cover almost the entire surface of the wafer, and then the vapor deposited layer 4 is used as a common electrode for plating. , A I is applied to the opening of the plating resist by electroplating.
Projections are formed on the I plating layer 5 to a thickness of 15 μm to 25 μm. Thereafter, the conventional method is to peel off and remove the metal resist, and then remove the vapor deposited layer 4 by etching the buffer layer 4b and the adhesive layer 4a in this order using the A II plating layer 5 as a resist to form an A11 bump. It was adopted by

Regarding the bump structure in the TAB mounting method mentioned above, many (combinations of gold layer materials) have been proposed as shown in Table 1, and the basic metal material composition in the bump structure is A metal layer that has high adhesive strength, low contact resistance, and has the effect of preventing the progress of interdiffusion between metals is disposed as the first layer as the adhesive layer 4a, and is used as a bump in the bonding process etc. A metal layer having the effect of relaxing and absorbing the stress applied to the IC is arranged as the second layer as a buffer layer 4b, and the bump structure of the IC in the form of a protrusion [All bumps] is formed by A I+ plating on the buffer layer 4b. Among the many combinations of bump structures shown in Table 1, the adhesive layer 4a and the buffer layer 4b are inexpensive and can be formed using a simple film forming technique such as resistance heating vapor deposition. Considering the combination of metal materials that can form the following, Cr was used as the adhesive layer 4a, and Ag was used as the buffer layer 4b, as explained based on FIG.

Table 1 However, according to the Au bump forming method in the prior art described above, when the vapor deposited layer 4 is removed by etching in the order of the buffer layer 4b and the adhesive layer 4a using the All plating layer 5 as a resist, the buffer layer 4b is formed. Since the etching speed of the Ag layer is fast, the buffer layer 4b is left in a shape that is equal to or slightly smaller than the root area of the Au plating layer 5. The etching time margin is narrow as side etching progresses, and in film formation using the resistance heating method, there is a 10% variation in the thickness of the evaporated film depending on the wafer set position in the evaporation equipment and the state of the evaporation source.
~20%, so the etching time difference is large, etc.
This has been an obstacle in progressing the automation of etching of the buffer layer 4b. When the adhesive layer 4a is subsequently etched, if the amount of side etching of the buffer layer 4b is large, the Ap pad 2 will be corroded by the etching solution of the adhesive layer 4a, leading to pattern breakage and the strength of the Au bumps being reduced. This caused quality and reliability problems such as deterioration.

As described above, the etching of the vapor deposited layer 4 in the prior art improves the automation of Au bump formation and the quality of All bumps.
This has been a major problem in improving reliability.

It is an object of the present invention to solve the problems in the prior art using the above-mentioned Cr--Ag combination and to provide a method for stably controlling etching of a deposited layer.

The gist of the present invention is to perform heat treatment after forming the All-plated layer and prior to etching the deposited layer.

The bump forming method according to the present invention will be explained below.

The bump structure in the present invention is the same as that in the prior art, and the difference between the present invention and the prior art is that after the Au plating layer 5 is formed and before the vapor deposition layer 4 is etched, it is etched under a temperature condition of 250° C. or more. The point is that heat treatment is performed for about 30 minutes at
By this heat treatment, an Ag--Au diffusion layer is formed between the Ag and Au plating layer 5 forming the buffer layer 4b.

Since the etching rate of the etching solution for Ag-Au diffusion layer FF14b is much slower than that of Ag, the lower part of the Au plating layer 5 where the Ag-Au diffusion layer is formed is a buffer layer 4b. For side etching with etching solution,
It has a wide etching time margin and is sufficiently tolerant of variations in the thickness of the vapor deposited layer 4, making it possible to realize etching automation and furthermore to form a stable Au bump without side etching. This makes it possible to form high-quality bumps without pattern breakage.

According to experiments, when Ag etching was carried out using a ferric nitrate aqueous solution as the etching solution for the Ag layer, the sample heat-treated at 250°G for 30 minutes was 115%, and the sample heat-treated at 300°G for 30 minutes was is 1/9. Sample heat treated at 350°G for 30 minutes is l/2
As a result, as shown in FIG. 2, it was confirmed that it was possible to stably control the etching shape of the lower part of the All-plated layer.

Further, when etching the Cr layer, using potassium ferricyanide/sodium hydroxide as an etching solution, stable etching is possible because the Ag layer has a resisting effect in the 61 layer etching.

As described above, according to the bump forming method according to the present invention, it is possible to stably etching a deposited layer with a wide margin, it can be automated to the level of Esochin, and it is also possible to obtain bumps of high quality. This makes it possible to establish a TAB implementation with low implementation cost and high reliability.

Furthermore, the present invention is also applicable to other mounting methods, such as face-down bonding solder bumps.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the bump structure in the prior art and the present invention, and FIG. 2 is a characteristic diagram showing the relationship between heat treatment temperature and etching rate of the Ag layer in the present invention. 1...IC1 2...A1 pad, 6...passivation film, 4...evaporation layer. 4a...Adhesive layer, 4b...Buffer single layer, 5...Au plating layer. (8) Words-1 Figure

Claims (1)

[Claims] In a method of forming a protruding electrode, a vapor deposited layer is formed on the entire surface of an IC, the vapor deposited layer is used as a common electrode, a protruding electrode is formed on the C pad, and the common electrode portion is removed by etching. 1. A method for forming a protruding electrode, which comprises applying a heat treatment to promote alloying of a vapor deposited layer and a material for the protruding electrode prior to etching away the portion of the protruding electrode.