JPS59104116A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59104116A
JPS59104116A JP57214975A JP21497582A JPS59104116A JP S59104116 A JPS59104116 A JP S59104116A JP 57214975 A JP57214975 A JP 57214975A JP 21497582 A JP21497582 A JP 21497582A JP S59104116 A JPS59104116 A JP S59104116A
Authority
JP
Japan
Prior art keywords
silicon
film
silicon dioxide
dioxide film
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57214975A
Other languages
Japanese (ja)
Other versions
JPH0441488B2 (en
Inventor
Tadashi Nishimura
正 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57214975A priority Critical patent/JPS59104116A/en
Publication of JPS59104116A publication Critical patent/JPS59104116A/en
Publication of JPH0441488B2 publication Critical patent/JPH0441488B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To contrive to enahance quality of the fusion recrystallized silicon layer of a semiconductor device when a silicon-on-insulator substrate is to be formed by a method wherein a thin silicon nitride film is formed on a thick silicon dioxide film as an insulating film thereof, and moreover an extremely thin silicon dioxide film is formed. CONSTITUTION:A silicon dioxide film 5 is formed on a silicon substrate 1. Then a thin silicon nitride film 6 is formed. Then phosphorus ions are implanted, and a heat treatment is performed in an oxidizing atmosphere to form an extremely thin silicon dioxide film 8 on the surface of the silicon nitride film 6. Then a polycrystalline silicon layer 3 to be performed with fusion recrystallization is formed. The polycrystalline silicon layer 3 thereof is fusion recrystallized according to the energy beam of laser or an electron beam, etc., and by converting the film into a single crystal or crystal grains, a proper surface protective film is formed.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置に関し、特に絶縁層上に良質な半
導体層を形成することができるシリコンオンインシュレ
ータ基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a silicon-on-insulator substrate on which a high-quality semiconductor layer can be formed on an insulating layer.

〔従来の技術〕[Conventional technology]

一般に、高速でかつ高信頼性の半導体装置にはシリコン
オンサファイヤ基板（以下ＳＯ８基板という）が用いら
れるが、このＳＯ８基板の代替品として、シリコンオン
インシュレータ基板（以下ＳＯＩ基板）が低価格、高品
質を期して開発がなされている。Generally, silicon-on-sapphire substrates (hereinafter referred to as SO8 substrates) are used for high-speed and highly reliable semiconductor devices, but as an alternative to this SO8 substrate, silicon-on-insulator substrates (hereinafter referred to as SOI substrates) are available at low cost and high cost. Developed with quality in mind.

第１図は従来の８０Ｉ基板の構造およびその製造方法を
示す断面図である。同図において、（１）はシＩＪ−１
ン基板、　ｆ２１１ｄシリコン酸化膜、（３）はアモル
ファスシリコン層または多結晶シリコン層、（４）はレ
ーザ、電子ビームなどのエネルギービームである。FIG. 1 is a sectional view showing the structure of a conventional 80I substrate and its manufacturing method. In the same figure, (1) is
(3) is an amorphous silicon layer or polycrystalline silicon layer; (4) is an energy beam such as a laser or an electron beam.

次に上記構成によるＳＯＴ基板の製造工程について説明
する。まず、シリコン基板（１）上に厚いシリコン酸化
膜（２）を形成する。そして、このシリコン酸化膜（２
）上にアモルファスシリコン層または多結晶シリコン層
（３）を形成する。そして、このアモルファスシリコン
層または多結晶シリコン層（３）をレーザビームあるい
は′ｉ６子ビームなどのエネルギ−ビーム（４）で溶融
再結晶させて、単結晶化または大結晶粒化させる。この
場合、ＳＯＳ基板のサファイヤに相当するものが、厚い
シリコン酸化膜（２）である。このシリコン酸化膜（２
）は非晶質であるため、サファイヤの場合のように、こ
の上に形成されたロセスに投入され、半導体装置を製造
することができる。Next, the manufacturing process of the SOT substrate with the above configuration will be explained. First, a thick silicon oxide film (2) is formed on a silicon substrate (1). Then, this silicon oxide film (2
) an amorphous silicon layer or a polycrystalline silicon layer (3) is formed thereon. Then, this amorphous silicon layer or polycrystalline silicon layer (3) is melted and recrystallized with an energy beam (4) such as a laser beam or an i6 beam to form a single crystal or a large crystal grain. In this case, the thick silicon oxide film (2) corresponds to the sapphire of the SOS substrate. This silicon oxide film (2
) is amorphous, so it can be put into a process formed on it to manufacture semiconductor devices, as in the case of sapphire.

なお、前記エネルギービームの代シに、走査型の細いヒ
ータを用いた〕、前記多結晶層が溶融の際に、はく離し
ないように、さらに誘電体の被着層で覆ってもよいこと
はもちろんである。Note that a thin scanning heater was used in place of the energy beam. It goes without saying that the polycrystalline layer may be further covered with a dielectric layer to prevent it from peeling off during melting. It is.

しかしながら、従来のＳＯＩ基板では厚い二酸化シリコ
ン膜の膨張率が溶融再結晶シリコンと大きく異なるため
、溶融再結晶シリコン層内へのひずみの残留、およびシ
リコンと二酸化シリコン膜とのぬれの悪さによってシリ
コン溶融時に生ずるシリコンのはく離の問題があり、Ｓ
ＯＩ基板の普及をさまたげている。そこで、シリコンと
のめれもよく、しかも、熱膨張率も近いシリコン窒化膜
を絶縁膜として使用すること、あるいは等価的に厚い絶
縁膜とするため、厚い二酸化シリコン膜上に薄いシリコ
ン窒化膜を形成することが提案されているが、いずれの
方法も、再結晶後のシリコンとシリコン窒化膜の界面に
電気的な準位が多く存在し、素子を形成した後のリーク
甫、流や長期の素子特性変動の原因になるなどの欠点が
あった。However, in conventional SOI substrates, the expansion coefficient of the thick silicon dioxide film is significantly different from that of molten recrystallized silicon, so the silicon melting may occur due to residual strain in the molten recrystallized silicon layer and poor wetting between the silicon and the silicon dioxide film. There is a problem with silicon peeling that sometimes occurs, and S
This is hindering the spread of OI substrates. Therefore, it is recommended to use a silicon nitride film as an insulating film, which has good compatibility with silicon and has a similar coefficient of thermal expansion, or to create an equivalently thick insulating film by forming a thin silicon nitride film on a thick silicon dioxide film. However, in both methods, many electrical levels exist at the interface between silicon and silicon nitride film after recrystallization, and leakage and current after the device is formed, as well as long-term This has drawbacks such as causing variations in device characteristics.

〔発明の概要〕[Summary of the invention]

したがって、この発明の目的は溶融再結晶シリコンとの
界面特性を向上することができ、しかも熱膨張係数が等
価的に窒化シリコン膜と考えることができ、高品質で大
面積のＳＯＩ基板を備えた半導体装置を提供するもので
ちる。Therefore, the purpose of the present invention is to improve the interface characteristics with molten recrystallized silicon, to have a thermal expansion coefficient that can be equivalently considered as a silicon nitride film, and to provide a high-quality, large-area SOI substrate. This company provides semiconductor devices.

このような目的を達成するため、この発明はシリコン半
導体基板主面上、または誘電体基板面上に形成した厚い
二酸化シリコン膜と、この厚い二酸化シリコン膜上に形
成した薄い窒化シリコン膜と、この薄い窒化シリコン膜
にイオンビームを）るいはイオン注入によ多形成した極
く薄い二酸化シリコン膜とから構成した多層の絶縁物層
上に溶融、再結晶されたシリコン層を形成するものであ
り、以下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention includes a thick silicon dioxide film formed on the main surface of a silicon semiconductor substrate or a dielectric substrate surface, a thin silicon nitride film formed on the thick silicon dioxide film, and a thin silicon nitride film formed on the thick silicon dioxide film. A silicon layer that is melted and recrystallized is formed on a multilayer insulating layer consisting of an extremely thin silicon dioxide film formed by applying an ion beam to a thin silicon nitride film or by ion implantation. This will be explained in detail below using examples.

〔発明の実施例〕[Embodiments of the invention]

第２図はこの発明に係る半導体装置の一実施例を示す断
面図である。同図において、（５）は厚み１．０μｍの
厚い二酸化シリコン膜、（６）は例えば７５０Ａの薄い
窒化シリコン膜、（７）は注入するリンイオン、（８）
は例えば１００八程度の極く薄い二酸化シリコン膜であ
る。FIG. 2 is a sectional view showing an embodiment of the semiconductor device according to the present invention. In the figure, (5) is a thick silicon dioxide film with a thickness of 1.0 μm, (6) is a thin silicon nitride film of, for example, 750A, (7) is a phosphorus ion to be implanted, and (8) is a thin silicon nitride film of 750A.
is, for example, an extremely thin silicon dioxide film of about 100 octane.

次に上記構成による半導体装置のＳＯＩ基板の製造工程
について第３図（ａ）〜第３図（ｄ）を参照して説明す
る。まず、第３図（ａ）に示すように、シリコン基板（
１１上に例えば厚み１．０μｍの二酸化シリコン膜（５
〕を形成する。次に、この二酸化シリコン膜（５１上に
例えば７５０Ａの薄い窒化シリコン膜（６１を形成する
。次に、第３図（ｂ）に示すように、リンイオン（７）
を注入するが、その注入電圧は２５ＫｅＶでｌＸｌ０”
／−程度の注入を行う。次に、酸化性雰囲気中で、９５
０℃、２０〜３０分の熱処理を行なうことにより、第３
図（Ｃ）に示すように、前記窒化シリコン（６１表面の
１００５−程度の極く薄い二酸化シリコン膜（８）が形
成される。次に、溶融再結晶されるべき多結晶シリコン
層（３）を形成する。そして、この多結晶シリコン層（
３）をレーザあるいは電子ビームなどのエネルギービー
ムで溶融再結晶させ、単結晶化または結晶粒化すること
により、適当な表面保護膜を形成することができる。Next, the manufacturing process of the SOI substrate of the semiconductor device having the above structure will be explained with reference to FIGS. 3(a) to 3(d). First, as shown in FIG. 3(a), a silicon substrate (
For example, a 1.0 μm thick silicon dioxide film (5
] to form. Next, a thin silicon nitride film (61) of, for example, 750A is formed on this silicon dioxide film (51.Next, as shown in FIG. 3(b), phosphorus ions (7)
The injection voltage is 25KeV and lXl0”
/- degree of injection is performed. Next, in an oxidizing atmosphere, 95
By performing heat treatment at 0°C for 20 to 30 minutes, the third
As shown in Figure (C), an extremely thin silicon dioxide film (8) of about 1005- is formed on the surface of the silicon nitride (61).Next, a polycrystalline silicon layer (3) to be melted and recrystallized is formed. Then, this polycrystalline silicon layer (
A suitable surface protective film can be formed by melting and recrystallizing 3) with an energy beam such as a laser or an electron beam to form a single crystal or crystal grains.

前記したように形成した基板で、シリコン層の溶融再結
晶化を行なうにあたって、多結晶シリコン層（３）の下
部には極く薄い二酸化シリコン膜（８）が形成されてい
るが、極く薄いため、熱的にはもう一層下の薄い窒化シ
リコン膜（６１が多結晶シリコン層（３）に接している
ことと等価である。したがって、溶融再結晶時に、シリ
コンが影響を受ける層は窒化シリコン膜であることから
、再結晶後のひずみ、再結晶時のはく離問題は窒化シリ
コン膜を絶縁膜として用いた場合と同程度の良さが実現
できる。When melting and recrystallizing the silicon layer on the substrate formed as described above, an extremely thin silicon dioxide film (8) is formed under the polycrystalline silicon layer (3). Therefore, it is thermally equivalent to the thin silicon nitride film (61) in contact with the polycrystalline silicon layer (3). Therefore, the layer where silicon is affected during melting and recrystallization is silicon nitride. Since it is a film, problems with distortion after recrystallization and peeling during recrystallization can be achieved to the same degree as when a silicon nitride film is used as an insulating film.

また、実際の界面はシリコンと二酸化シリコン膜によっ
て構成されるため、界面準位の存在はほとんどなく、電
気的には良好な界面特性を得ることができる。Further, since the actual interface is composed of silicon and a silicon dioxide film, there is almost no interface state, and electrically good interface characteristics can be obtained.

なお、上記実施例ではリンのイオン注入による窒化シリ
コン膜の増速酸化という手法を用いて、窒化シリコン膜
上に極〈薄い二酸化シリコン膜を形成したが、これに限
定せず、例えばクラスターイオンビームなどを用いても
よいことはもちろんである。また、シリコン基板を用い
たが誘電体基板を用いてもよいことはもちろんである。In the above embodiment, an extremely thin silicon dioxide film was formed on the silicon nitride film using a method of accelerated oxidation of the silicon nitride film by ion implantation of phosphorus, but the method is not limited to this, and for example, cluster ion beam Of course, you may also use the following. Furthermore, although a silicon substrate is used, it goes without saying that a dielectric substrate may also be used.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、この発明に係る半導体装置
によればＳＯＩ基板の形成にあたり、その絶縁膜として
、厚い二酸化シリコン膜の上に薄い窒化シリコン膜を形
成し、さらにその上に極〈薄い二酸化シリコン膜を形成
する構造をとることにより、溶融再結晶シリコン層の品
質が向上し、電気的特性も優れるなどの効果がある。As explained in detail above, according to the semiconductor device according to the present invention, when forming an SOI substrate, a thin silicon nitride film is formed on a thick silicon dioxide film as an insulating film, and an extremely thin By adopting a structure in which a silicon dioxide film is formed, the quality of the molten recrystallized silicon layer is improved and electrical characteristics are also excellent.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＳＯＩ基板の構造およびその製造方法を
示す断面図、第２図はこの発明に係る半導体装置の一実
施例を示す断面図、第３図（ａＪ〜第３図（ｄ）は第２
図に示す半導体装置の製造工程を示す断面図である。 （１）・１１１１・シリコン基板、　ｆ２）−・自・シ
リコン酸化ＪＩＥ、　（３）・・・・アモルファスシリ
コン層マタは多結晶シリコン層、（４）・・・・エネル
ギービーム、（５）・・・・厚い二酸化シリコン膜、（
６）・・・・薄い窒化シリコン膜、　（７）・・・・リ
ンイオン、（８）・拳・・極〈薄い二酸化シリコン膜。 なお、図中、同一符号は同一または相当部分を示す。 代理人　　葛　野　信　− 第１図 第２０ 第３図 １１１↓↓↓↓〜７ 手続補正書（自発） 特許庁長官殿 １、事件の表示　　　　′Ｐ？願昭　５７−２１４９７
５号２、発明の名称 半導体装置 ３、補正を−（−る者 ５、補正の対象 明細書の発明の詳細な説明の掴 ６　補正の内容 明細書第６頁第８行の「表面保誇膜」を「素子を形成す
べき半導体層」と補正する。 以　　上FIG. 1 is a sectional view showing the structure of a conventional SOI substrate and its manufacturing method, FIG. 2 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. is the second
FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in the figure. (1)・1111・Silicon substrate, f2)-・Self-silicon oxidation JIE, (3)・・・Amorphous silicon layer base is polycrystalline silicon layer, (4)・・・Energy beam, (5)・・・・Thick silicon dioxide film, (
6) Thin silicon nitride film, (7) Phosphorus ion, (8) Fist... Extremely thin silicon dioxide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1, Figure 20 Figure 3, 111↓↓↓↓～7 Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1. Indication of the case 'P? Gansho 57-21497
No. 5 No. 2, Name of the invention Semiconductor device 3, Amendment made by - (5, Detailed description of the invention in the specification to be amended 6 Contents of the amendment "film" is corrected to "semiconductor layer on which an element is to be formed."

Claims (1)

【特許請求の範囲】 （１１シリコン半導体基板主面上、または誘電体基板面
上に形成した厚い二酸化シリコン膜と、この厚い二酸化
シリコン膜上に形成した薄い窒化シリコン膜と、この薄
い窒化シリコン膜にイオンビームあるいはイオン注入に
よ）形成した極く薄い二酸化シリコン膜とから構成した
多層の絶縁物層上に溶融、再結晶化されたシリコン層を
形成したことを特徴とする半導体装置。 （２）前記薄い窒化シリコン膜の厚みは２．０００Ａ以
下、極く薄い二酸化シリコン膜は３００八以下であるこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
。[Claims] (11) A thick silicon dioxide film formed on the main surface of a silicon semiconductor substrate or a dielectric substrate surface, a thin silicon nitride film formed on the thick silicon dioxide film, and a thin silicon nitride film formed on the thick silicon dioxide film. A semiconductor device characterized in that a silicon layer that has been melted and recrystallized is formed on a multilayer insulating layer that is made up of an extremely thin silicon dioxide film formed (by ion beam or ion implantation). (2) The semiconductor device according to claim 1, wherein the thin silicon nitride film has a thickness of 2.000A or less, and the extremely thin silicon dioxide film has a thickness of 300A or less.
JP57214975A 1982-12-06 1982-12-06 Semiconductor device Granted JPS59104116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57214975A JPS59104116A (en) 1982-12-06 1982-12-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57214975A JPS59104116A (en) 1982-12-06 1982-12-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59104116A true JPS59104116A (en) 1984-06-15
JPH0441488B2 JPH0441488B2 (en) 1992-07-08

Family

ID=16664643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57214975A Granted JPS59104116A (en) 1982-12-06 1982-12-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59104116A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100349184B1 (en) * 1997-12-26 2002-12-16 엠이엠씨코리아 주식회사 Wafer attach method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56112743A (en) * 1980-02-12 1981-09-05 Chiyou Lsi Gijutsu Kenkyu Kumiai Thin film semiconductor device and manufacture thereof
JPS56116627A (en) * 1980-02-20 1981-09-12 Chiyou Lsi Gijutsu Kenkyu Kumiai Thin film semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56112743A (en) * 1980-02-12 1981-09-05 Chiyou Lsi Gijutsu Kenkyu Kumiai Thin film semiconductor device and manufacture thereof
JPS56116627A (en) * 1980-02-20 1981-09-12 Chiyou Lsi Gijutsu Kenkyu Kumiai Thin film semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100349184B1 (en) * 1997-12-26 2002-12-16 엠이엠씨코리아 주식회사 Wafer attach method

Also Published As

Publication number Publication date
JPH0441488B2 (en) 1992-07-08

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