JPS59103378A - Insulated gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To expand the applied voltage range between a source and a drain by a method wherein a Pt layer and a back-gate electrode are superposed on the side of a p type Si substrate, a p<+> layer is formed on the side reverse to the channel side adjoining to the n<+> type source located on the other side of the p type Si substrate, and it is connected to the back gate electrode. CONSTITUTION:A p<+> layer 10 and a back-gate electrode 11 are formed on one surface of a p type Si substrate, and an n<+> type source layer 3, a drain layer 4 and a p<+> type layer 15, adjoining to the n<+> layer 3, are formed on the other surface of the p type Si substrate. An aperture is opened on an insulating film 2, an electrode 8 is attached astriding a source layer 13 and the p<+> layer 15, connected to the back-gate electrode 11, and a drain electrode 9 and an insulating gate electrode 7 are attached. When the voltage of the electrode 9 is increased for the electrode 8, the hole generated at a high electric field region 12 runs to the electrode 8 through a p-layer 1 and the p<+> layer 15, or runs to the electrode 11 through the p-layer 1 and a p<+> layer 14, thereby enabling to lower the boosting of potential located in the vicinity of a region 12 and also to lower the forward bias of the junction 13 of the n<+> layer 13 and the p type substrate 1. As a result, the range of voltage which can be applied between the electrode 8 and the drain electrode 9 can be widened when compared with the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in insulated gate field effect transistors.

(Prior Art) Conventionally, as shown in FIG. 1, as shown in FIG.
and 4 are provided, and a semiconductor region 5 surrounded by semiconductor regions 3 and 4 is formed on the main surface 2 side of the semiconductor region 1, and on the surface of the region 5 of the semiconductor region 1 on the main surface 2 side. An isoelectric layer 7 is disposed on the semiconductor region 3 through an insulating layer 6, and a conductive layer 8 is ohmically provided on the main layer of the semiconductor region 3 on the I+2 side. A conductive layer 9 is ohmically formed on the surface of the surface 2, and a conductive layer 16' is ohmically attached to the surface of the semiconductor region 1 on the main surface 2.
Due to the dry structure, the semiconductor region 3 is used as a source region,
Semiconductor region 47 is a drain region, semiconductor region 1 is a channel forming region, insulating layer 6 is a gate insulating layer, conductive layers 7, 8 .
9 and 16', n:f: receiver electrode, source electrode,
A structure having a drain electrode and a backgate electrode has been proposed.

However, in the case of the insulated gate field-effect l syndistor shown in FIG. 1, the conductive layer 8 as the source electrode and the isoelectric layer 16' as the backgate electrode are shortened. 2# = When a voltage greater than a positive predetermined value (threshold value) is applied to the conductive layer 7 with respect to the conductive layer 8 as a source electrode, the region 5 of the semiconductor region l as a channel forming region is applied. An N-type layer is formed on the surface of the main surface 2, and a full positive voltage is applied to the conductive layer IC as a drain electrode and the conductive layer 8 as a source electrode.
'L is formed in the conductive layer 8, the semiconductor region 3, and the main surface 2 side of the region 5 of the semiconductor region 1, and a current path connected to the channel of the 1LkN type layer, the semiconductor region 4, and the conductive layer 9 is formed. However, when the positive voltage applied to the conductive layer 8 as the source electrode and the d conductive layer 9 as the drain electrode is increased, the semiconductor region 1 is turned on. A crystal electric field region is formed in the portion of the semiconductor region 4 on the semiconductor region 3 side, and a crystal electric field region is formed on the surface m1 of the main surface 21111 of the semiconductor region 5. However, impact ionization occurs in the electric field region 12, which causes the generation of electron-hole pairs, and the generated holes are transferred not only to the semiconductor region 1 but also to the conductive layer 16 as a backgate. blf: TL ;b Therefore, due to the resistance of the semiconductor region l, the potential near the region 12 of the semiconductor region l becomes
The conductivity is higher (positive) than the conductive layer 8 as the backgate electrode and the conductive layer 8 as the source electrode, thus the rectification formed by the semiconductor region 1 and the semiconductor region 3 as the source chain acid. The sexual junction 13 is biased in the forward direction, and the injection of electrons from the semiconductor region 3 serving as a source region to the semiconductor region l is promoted. The control function of the device is limited by the positive feedback effect of generating a pair, and the voltage can be applied between the conductive layer 8 as the source pole and the conductive layer 9 of C as the drain pole. ``The disadvantage is that the voltage is limited and the voltage is limited.''

(Object of the Invention) The present invention has been proposed in order to eliminate this drawback, and it is possible to suppress the rise in potential near the region 12 of the semiconductor region 1 shown in FIG. 1 to a low level. The overall purpose is to improve the voltage range by applying the same VC to the source and drain electrodes.

(Structure of the Invention) In order to achieve the above-mentioned object, the present invention includes a first semiconductor region having a first conductivity type; and a second semiconductor region having a higher specific resistance than the first semiconductor region;
A third semiconductor region serving as a source region having a second diagonal turtle shape opposite to the first semiconductor region to which the semiconductor region VC is connected is connected to the first and third semiconductor regions; a fourth semiconductor region as a drain region spanning a second conductivity type (connected to the first Nr2 second semiconductor region), and a gate insulating layer on the surface of the region between the third and fourth semiconductor regions. a 10th isoelectric layer as a gate electrode, and a 10th isoelectric layer as a gate electrode, and a 10th isoelectric layer as a gate electrode, and
The semiconductor regions V are not connected and are provided on the surface of the main surface opposite to the second semiconductor region in the first semiconductor head, and have a second conductive property as a back gate electrode. In the insulated gate field effect transistor comprising a layer, the first conductivity type is not connected to the first and fourth semiconductor regions, but is connected to the second and thirtieth semiconductor regions, and has a first conductivity type. ] and a fifth semiconductor region having a specific resistance lower than that of the second semiconductor region, and a third conductive region connected to the second and fifth semiconductor regions and serving as a common electrode. The gist of the invention is to provide an insulating gate type 'turret field effect transistor' having a layer structure.

Furthermore, the present invention includes a first semiconductor region having a first conductivity type, and a semiconductor region connected to the first semiconductor region having a first conductivity type. a second semiconductor region having a completely cured resistivity, and a third half body as a source region having a second isoelectric type opposite to that of the first semiconductor region connected to the second semiconductor region; a fourth semiconductor region that is not connected to the first and third semiconductor regions but is connected to the second semiconductor region and serves as a fully cured drain region of the second conductivity type; and an insulation If! as a gate insulation layer on the surface of the region between the fourth semiconductor regions. A first conductive layer serving as a gate electrode is disposed through a first conductive layer VCB, and a first conductive layer VCB is connected to the third and fourth semiconductor regions VCB and The second layer 1M serves as a γ-shaped back gate electrode provided on the surface of the main surface opposite to the semiconductor region of No. 2.
In the e-bayashi gate type field effect syndister with ii+,
The fourth semiconductor region is connected to the first, second and third semiconductor regions, has a first conductivity type, and has a resistivity lower than that of the second semiconductor region. An insulating cat type field effect transistor according to the invention, characterized in that it has a fifth semiconductor region having a structure of 1, and a third conductive a layer as a common electrode connected to the third and fifth semiconductor regions. This is a summary.

In particular, the present invention includes a first semiconductor region having a first conductivity type, and a first semiconductor region connected to the first semiconductor region, having a first conductivity type and having a higher ratio than the first semiconductor region. a second semiconductor region having resistance; a third semiconductor region serving as a source region having a second conductivity type opposite to that of the first rod-conducting region connected to the second semiconductor region; a second conductivity type 7f connected to the second semiconductor region; a fourth semiconductor region serving as a southward drain region; An insulating layer as a gate insulating layer on the surface of the region between the semiconductor regions of No. 4? The first conductive layer as a gate electrode is disposed through the first conductive layer, and the second conductive layer is not connected to the third and fourth semiconductor regions, but is connected to the first conductive layer as a gate electrode.
A second conductive layer serving as a back gate electrode is provided on the surface of the main surface opposite to the second semiconductor region in the semiconductor region of the insulated gate field effect transistor. In the third semiconductor region, the surface of the third semiconductor region is changed;
A U-shaped, V-shaped, rectangular, etc. groove reaching the second and third semiconductor regions, and a third conductive layer connected to the second and third semiconductor regions is provided on the surface of the ridge. This is an insulated gate field effect transistor characterized by the gist of the invention.

I will briefly explain the drawings of the uninvented examples. 12
The embodiments are just examples, and it is not a stretch to make individual changes or improvements without departing from the spirit of non-invention.

FIG. 2 shows a first embodiment of an insulated gate field effect transistor according to the present invention. Parts corresponding to those in FIG. In the configuration shown in FIG. 2, semiconductor region 1 is used as a Nayanel formation region.
A P-type semiconductor region 14 is formed on the concave main surface 170 on the opposite side to the main surface 2J1j, and a P-type semiconductor region 14 is formed on the main surface 1O on the opposite side to the main surface 1IIJ17 in the semiconductor region 14. The conductive layer 11 i as a backkate electrode L pole
A P-type semiconductor region 15 is formed in the semiconductor region 2 as a source region and on the opposite side of the region 51iltl of the semiconductor region 1 so as to be in instant contact, and a conductive region 15 is formed as a source and backgate common electrode. The structure is the same as that shown in FIG. 1 except that the conductive layer 8 is formed on the surface of the semiconductor region 3 and the semiconductor region 15 (i21) 411. However, in this case, the semiconductor region 15 is positioned as close to the high electric field region 12 of the semiconductor region 1 as possible.

The above is the configuration of the first embodiment of the insulated gate field effect transistor according to the present invention.
Since L has the same structure as in Fig. 1 except for the Φ term mentioned above, the important details are omitted, but the common '
Let's briefly remember the conductive layer 8 as the electrode and the hysterically conductive layer 11 as the backgate electrode, and the isoelectric layer 7V as the gate electrode and the conductive layer 8 as the common electrode. Is the voltage bigger than the positive limb value (threshold 11)? Give, Teyai
A channel of an N-type layer is formed on the main surface 2 side surface of the region 5 of the semiconductor region 1 as a layer forming region, and a conductive layer 9 as a common electrode is formed on the conductive layer 9 as a drain electrode. A positive voltage is applied to 8 to form a channel of an N-type layer 8 on the surface of the i-conductive layer 8, the half-core region 3, and the main surface 2 side of the region 5 of the semiconductor region 1; Semiconductor region 4, conductor'
A current path connected to the conductive layer 9 is formed, and the device is in the on state as in the case shown in FIG.

However, in the case of the insulated gate type Amali effect transistor according to the present invention shown in FIG. 2, in the on state, ' If the voltage is added fC, then the first
As explained in FIG. The resistance of the semiconductor region 1 and the semiconductor region 14 is lower than that of the case described in FIG. 1. In other words, the potential rise near the cylindrical electric field region 12 is low, which means that the forward bias of the junction 13 formed between the body region 3 and the semiconductor region 1 is lowered. Therefore, the voltage that can be applied between the conductive layer 8 as a common electrode and the conductive layer 9 as a drain electrode is smaller than that in the conventional insulated gate field effect transistor shown in FIG. It has the effect of being able to reduce

Next, referring to FIG. 3, a second embodiment of the insulated gate field effect transistor according to the present invention will be described.
As an example of the configuration shown in Figure 2, VC7TI:
The configuration is the same as that shown in FIG. 2, except that the P-type semiconductor region 15 can be formed from the main area 2 of the semiconductor region 1 to the semiconductor region 14 rather than later.

The above is the second embodiment of the insulated gate type boosting effect transistor of the present invention.
However, except for the above-mentioned drawbacks, the structure is the same as that shown in FIG. 2, so a detailed explanation will be omitted. The S conductive layer 8 is filled through the semiconductor region 1 and the semiconductor region 15i, or the conductive layer 11 as the second bank electrode is passed through the semiconductor region 1 and the semiconductor region 14. Therefore, the resistance is smaller than in the case described above in FIG. Since it is possible to reduce the degree of It has the advantage of being more commercially available than red transistors.

Next, referring to FIG. 4, a third embodiment of the insulated gate field effect transistor according to the present invention will be described. In the structure shown in FIG.
Main surface 17 of 1 (1) opposite to main surface 211111 of
), a P-type semiconductor region 14 is formed on the surface, and a second backgate' electrode 4 is formed on the main surface 10 on the opposite side from the main surface 17 of the semiconductor region 14. A U-shape that forms the conductive layer 11 and extends from the semicircular region 3 to the semiconductor region 1 from the surface on the main surface 2 side of the semiconductor region 3 serving as a source region;
All 16 grooves such as V-shaped or rectangular are formed, and then 1
6 is the same as that shown in FIG. 2, except that a conductive layer 8 is formed as a common electrode so as to be in contact with both the semiconductor region 3 and the semiconductor region l. i, have a meeting. The groove 16 is located as close as possible to the semiconductor area 1 (7) and the turtle area 12.

The above is the configuration of the third embodiment according to Honkokiri, but because of this configuration, the IL has the same structure as the case of FIG. 1 except for the matters mentioned above. , the detailed explanation is omitted, or the conductive layer 8 as a common electrode and the conductive layer 11 as a back electrode are short-circuited, and the conductive layer 7 as a gate electrode is connected to the conductive layer 8 as a common electrode. VL
Applying a voltage greater than the value (threshold value) of the positive limb on the other hand,
A layer of an N-type layer is formed on the main surface 2 side of the region 5 of the semiconductor region 1 as a channel forming region, and a layer 6 as a common electrode is formed on the conductive layer 9 as a drain electrode. A positive voltage is applied to the conductive layer 8 and f'L is the main UII of the conductive layer 8, the semiconductor region 3, and the region 5 of the semiconductor region 1.
Nayanenope semiconductor region 4 formed on the surface of J2 side,
A path is formed that continues to the conductive layer 9, and the ON state is maintained as in the case of FIG.

However, in the case of the insulated gate field effect transistor according to the present invention shown in FIG. If a positive voltage is applied,
In the same way as shown in FIG. 1, the holes generated in the electrophoresis region 12 of the semiconductor region 1 flow through the entire semiconductor region 1 to the static layer 8 serving as a common electrode. Therefore, compared to the case of FIG. 1, the resistance due to the semiconductor region 1 is smaller, the potential rise near the high electric field region 12 is lowered, and the junction formed between the neck semiconductor region 3 and the semiconductor region 1 is reduced. 13
It is possible to reduce the degree of forward bias of /), so
The voltage that can be applied between the conductive layer 8 as the common electrode and the conductive layer 9 as the drain electrode is much higher than that in the conventional insulated gate field effect transistor shown in FIG. It has the effect of being able to do a lot of things.

Next, a fourth embodiment of the insulated gate type small field effect transistor according to the present invention will be described with reference to FIG. 5. In the structure shown in FIG. Formation formula 71. 4.
It has the same configuration as the case shown in the figure.

The above is the fourth embodiment of the insulated gate field effect transistor according to the present invention.
What can be said above? f: Same as in the case of FIG. 4 except f: The hole M is completely cured, so a detailed explanation will be omitted, but holes generated in the commercial electric field region 12 of the semiconductor region l are transferred to the S conductive layer as a common electrode. 8, the resistance due to the semiconductor region 1 is smaller than that shown in FIG. Since it is possible to fully image the IWi bias of the junction 13 formed with the region l,
This transistor has the effect that the voltage that can be applied between the conductive layer 8 serving as the common electrode and the conductive layer 9 serving as the drain electrode can be higher than that in the conventional insulated gate field effect transistor shown in FIG. It is.

Next, referring to FIG. 6, a fifth embodiment of the optical gate type field effect transistor will be described. f'Lfc
A conductive layer 8 as a common electrode and a semiconductor region 1. A P-type semiconductor region 18 is provided between the half-body region 3 and the semiconductor region 14.
The configuration is similar to that in Figure 5, except that A is in the form A).

The above is the fifth embodiment of the insulated gate field effect transistor according to the present invention, and with this configuration, 7'L has the same configuration as in the case of FIG. 5 except for the above-mentioned item 4. 7, so the explanation is omitted, the holes generated in the high electric field region 12 of the semiconductor region 1 follow the semiconductor region 1 and the semiconductor region 18 to the conductive layer 8 serving as a common electrode, and become redundant. Therefore, compared to the case shown in Fig. 1, the resistance is smaller and the potential rise near the a'+Q boundary region is lower.
Since it is ThJ capability to fully image the degree of deceptive bias of the contact layer 13 formed by the semiconductor region 3 and the semiconductor region 1 formed by X-&, the conductive layer 8 as a common electrode and the conductive layer 8 as a drain electrode This has the effect that the voltage that can be applied between the S-conducting layer 9 and the S-conducting layer 9 can be made higher than that of the conventional insulated gate field effect transistor shown in FIG.

Next, referring to FIG. 7, a sixth embodiment of the insulated gate field effect transistor according to the present invention will be described.
The insulated gate field effect transistor that performs all the operations of lAt is a single insulated gate field effect transistor with the configuration shown in Figure 1, and a large number of these single transistors are formed on the same substrate, and these are operated in parallel. However, as shown in FIG. 7, similarly to the first to fifth embodiments of the present invention, the semiconductor region 14 and the 2!3L conductive layer 11 are formed, and then the above-mentioned Single insulated cable type electric
One out of every few field effect transistors has a structure in which the insulated gate field effect transistors of the first to fifth embodiments shown in FIGS. 2 to 6 are all mixed. (
In FIG. 7, Tr2 and Tr3 are the first embodiment according to the present invention.

+1r, l Tr6 is a conventional disconnected gate field effect transistor. ) The above is the configuration of the sixth embodiment according to the present invention.
Even for conventional insulated gate field effect transistors such as Tr, , 'fr11, the semiconductor region connected to the four-conductor layer 8 as a common electrode of insulated gate field effect transistors Tr2 and Tr3 according to the present invention. The effect of reducing resistance due to 15 appears.7L, when looking at the entire element,
The source electrode and common electrode of a single insulated gate field effect transistor are connected to the source terminal and the drain electrode t.
This has the advantage that the voltage that can be applied between the fixed drain terminals can be made higher than that of the conventional method.

(Effects of the Invention) As explained above, in the insulated gate field effect transistor by Yuki Kinoe, fL is the voltage that can be applied between the source electrode and the drain electrode, or between the source terminal and the drain terminal. Since the structure can be made more compact, it is effective in increasing the withstand voltage of insulated gate field effect transistors.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a conventional insulated gate field effect transistor, and FIGS. 2 and 3. 4, 5, 6 and 7 respectively show the first insulated gate field effect transistor according to the present invention. Second. Third. 4th. It is a line sectional view showing a fifth and a sixth example. l...P4 type half region (second semiconductor region)
2...Main surface 3...N-type semiconductor region (third semiconductor region) 4
・・・・・・ 〃 (Fourth semiconductor region) 5.
... Semiconductor region 6'' ... Insulating layer 7 ... Conductive layer (lth conductive layer) 8 ...
・・ 〃 (Silk, 1 (7) conductive layer) 9 ・・・・
...〃 lO ... Main surface 11 ... Conductive layer (second conductive layer) L ...
. . . High electric field region 13 . . . Rectifying junction 14 . . . - P-type semiconductor region (first semiconductor region)
15...P-type semiconductor region (fifth semiconductor region)
16... Groove l7... Main ■ 18... P+ type semiconductor region (fifth semiconductor region) Patent applicant Nippon Telegraph and Telephone Public Corporation Figure 1 Figure 3 Figure 4 figure

Claims (1)

[Scope of Claims] The second region has a specific resistivity compared to the semiconductor region of l.
a third semiconductor region as a source region having a second conductivity type opposite to that of the first semiconductor region connected to the second semiconductor region, and the first and third semiconductor regions. a fourth semiconductor region as a drain box region having a second conductivity type that is not connected to the second semiconductor region and is connected to the second semiconductor region, and on the surface of the region between the third and fourth semiconductor regions; an insulating layer 7t as a gate insulating layer, a first (1) isoelectric layer as a gate electrode, and a first (1) isoelectric layer as a gate electrode;
A second back gate electrode connected to the third and fourth semiconductor regions and provided on the main surface of the first semiconductor region opposite to the second semiconductor region.
In the insulated cat type Amami-effect transistor, which is completely equipped with an isotropic layer, the first and fourth semiconductor regions (C are not connected and are connected to the second and third semiconductor regions, a fifth semiconductor region having a resistivity lower than that of the second semiconductor region, and a common semiconductor region connected to the second and fifth semiconductor regions; The third flexible layer as an electrode is characterized by a gate-type 'kame field effect transistor'. (2) The first conductivity type is semiconductor field,
a second semiconductor region connected to the first semiconductor region, having a conductive shape and having a resistivity In- opposite to the first semiconductor region; concatenated with
a third semiconductor region serving as a source region having a second conductivity type opposite to that of the semiconductor region; a third semiconductor region connected to the first and third semiconductor regions; A fourth semiconductor region as a drain region having two conductivity types, and an insulating layer disposed on the surface of the region between the third and fourth semiconductor regions.
a first conductive layer as a gate conductor;
．． A backgate electrode that is not connected to the third and fourth semiconductor regions and is provided on the main surface of the first semiconductor region VC on the side opposite to the second semiconductor region. In an insulated gate field effect transistor comprising all the conductive layers of the first and second conductive layers, the first and second conductive layers are not connected to the fourth semiconductor region; a fifth semiconductor region connected to the second and third semiconductor regions and having a first conductivity type and a lower resistivity than the second semiconductor region; a third electrically conductive layer as a common electrode connected to a semiconductor region of the insulated gate type 'katele effect transistor'. (3) a first semiconductor region having a first conductivity type, which is connected to the first semiconductor region and has a conductivity type η) having a higher ratio than the first semiconductor region; a second semiconductor region having resistance; a third semiconductor region as a source region having a second conductivity type opposite to that of the semiconductor region of steel connected to the second semiconductor region; A second semiconductor region that is not connected to the third semiconductor region but is connected to the second semiconductor region.
a fourth semiconductor region as a drain region having a conductivity type of a first electrically conductive layer; a bank gate electrode not connected to the third and fourth semiconductor regions, provided in the first semiconductor region on the surface of the main surface opposite to the second semiconductor region; In an insulated gate military field effect transistor comprising a second conductive layer, a U-shaped or V-shaped conductive layer extends from the surface of the third semiconductor region to the second and third semiconductor regions. , rectangular etc. bay r
An insulated cat cage field effect transistor, characterized in that a third conductive layer is provided on the surface of the ridge to the south and connected to the second and third semiconductor regions. (4) a first semiconductor region having a first conductivity type, and a semiconductor region having a first conductivity type 7 connected to the first semiconductor region and having a semiconductor region having a first conductivity type 7; 2nd resistivity
a semiconductor region connected to the second semiconductor region, a third semiconductor region as a source region having a second conductivity type opposite to that of the first semiconductor region, and the first and third semiconductor regions. a fourth semiconductor region serving as a drain region having a second conductivity type that is not connected to the second semiconductor region and connected to the second semiconductor region; and a surface of a region between the third and fourth semiconductor regions. a first conductive layer serving as a gate electrode fL7 disposed through an insulating layer serving as a gate insulating layer; Third
and a second backgate electrode not connected to the fourth semiconductor region but provided on the main surface of the first semiconductor region and opposite to the second semiconductor region. In an insulated gate field effect transistor fully equipped with a conductive layer, from the surface of the third semiconductor region, the first
．． It has U-shaped, V-shaped, rectangular, etc. grooves reaching the second and third semiconductor regions, and has a third conductive layer formed on the bottom surface of the ridges and connected to the first, second and third semiconductor regions. Claim 3. ! 15. The insulated gate field effect transistor according to 14. (5) a first semiconductor region having a first conductive turtle shape, connected to the first semiconductor region, having a conductivity type of the first conductivity type and having a commercial ratio compared to the first semiconductor region; The second semiconductor region having a high resistance and the first semiconductor region connected to the second semiconductor region have a second conductivity type opposite to each other. a third semiconductor region as a source region of 11", and a drain region of conductivity type 2 that is not connected to the first and third semiconductor regions but is connected to the second semiconductor region; a fourth semiconductor region, and a first conductive layer as a gate electrode disposed on the surface of the region between the third and fourth semiconductor regions with an insulating layer as a gate insulating layer interposed therebetween. and the second semiconductor region is not connected to the third and fourth semiconductor regions, is located in the first semiconductor region, and is provided on the surface of the main surface on the opposite side from the second semiconductor region. Second as back gate electrode
In an insulated gate field effect transistor comprising a conductive layer, a U-shaped, ■-shaped, rectangular shape extending from the surface of the third semiconductor region to the first, second, and third semiconductor regions. The first groove is formed on the surface of the cough groove. a fifth semiconductor region connected to the second and third semiconductor regions, having a conductivity type and having a specific resistance r lower than that of the second semiconductor region; 5. The insulated case 1 type military red transistor as claimed in claim 4, characterized in that the third conductive layer serves as a common electrode connected to the semiconductor region.