JPS5910008A - Power amplifier - Google Patents

Power amplifier

Info

Publication number
JPS5910008A
JPS5910008A JP57117832A JP11783282A JPS5910008A JP S5910008 A JPS5910008 A JP S5910008A JP 57117832 A JP57117832 A JP 57117832A JP 11783282 A JP11783282 A JP 11783282A JP S5910008 A JPS5910008 A JP S5910008A
Authority
JP
Japan
Prior art keywords
output
collector
collector loss
loss
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57117832A
Other languages
Japanese (ja)
Inventor
Hideyasu Jikou
秀保 慈幸
Katsuhiko Higashiyama
勝比古 東山
Takeshi Sato
剛士 佐藤
Kazuo Toda
戸田 一雄
Shizuyoshi Matsubara
松原 静喜
Takashi Fujii
喬 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57117832A priority Critical patent/JPS5910008A/en
Publication of JPS5910008A publication Critical patent/JPS5910008A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/307Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in push-pull amplifiers

Abstract

PURPOSE:To suppress the variation of a bias current due to the fluctuation of collector loss of an output transistor (TR), by providing a means to calculate the collector loss of the output TR from an output signal and a means to control the bias voltage of an output stage in response to the collector loss. CONSTITUTION:When output TRs Q1 and Q2 have a change of their collector losses, the difference between vias voltage V1 needed to the output TR and vias voltage V2 applied by a bias TRQ3 is set as V(Pc)=V1-V2=K.theta(Pc max.-Pc). In this case, Pc shows the collector loss of the output TR, and K is a constant. As a result, an output is converted into the collector loss Pc at a collector loss calculating circuit 6. Then a bias voltage control circuit 7 supplies V(Pc) on the basis of the loss Pc. Thus, the variation of a bias current due to the collector loss of the TRs Q1 and Q2 is prevented.

Description

【発明の詳細な説明】 産業上の利用分野 本光明d1、シングル・エンテッド・フノゾユノ0ル(
以下5EPPと略称する)出力段を備えた電力増幅器に
関するものである。
[Detailed description of the invention] Industrial application field
This invention relates to a power amplifier equipped with an output stage (hereinafter abbreviated as 5EPP).

従来例の構成とその問題点 第1図は、従来の5EPP回路の一例を示しだものであ
り、QlおよびQ2は出力トラノノスタ、Q:3はバイ
アス用トランジスタ、R1お、J:ヒR2fdバイアス
設定抵抗器である。端子1.2はドライバ段に接続され
、端子3,4は電源に接続される。
Conventional configuration and its problems Figure 1 shows an example of a conventional 5EPP circuit, where Ql and Q2 are output trannostars, Q:3 is a bias transistor, R1, J: R2fd bias setting. It is a resistor. Terminal 1.2 is connected to the driver stage and terminals 3, 4 to the power supply.

端子5は出力端である。Terminal 5 is an output terminal.

このように構成された従来例において、仮に、バイアス
用トランジスタQ 3と出力トラ7ノスタQl 、Q2
のVbc −Icの監度特性が全く同じものとすると、
周囲温度の変化に対しては・ぐイアス、[電流の変化は
全く起きない。しかし、出力信号が変rヒして出力トラ
ンジスタQl 、Q2のコレクタ損失が変化した場合、
出力トランノスタQl、Q2とバイアス用トランジスタ
Q;3どは熱的に結合さり、ではいるが、その間に必ず
熱抵1fLがあるため、両晋間の温度差が変化し、従っ
て・ぐイアスミMR,が変化してしまうという問題があ
った。
In the conventional example configured in this way, suppose that the bias transistor Q 3 and the output transistor 7 nostar Ql, Q2
Assuming that the monitoring characteristics of Vbc - Ic are exactly the same,
For changes in ambient temperature, no change in current occurs. However, if the output signal changes and the collector losses of the output transistors Ql and Q2 change,
The output trannostars Ql and Q2 and the bias transistor Q; 3 and 3 are thermally coupled, but since there is always a thermal resistance of 1fL between them, the temperature difference between the two sides changes, and therefore, Guiasumi MR, There was a problem that the .

発明の目的 そこで本発明は、出力信号から出力1・、/7ノスタの
コレクタ損失を算出する手段と、とのコレクタ損失に応
じて出力段のバイアス電圧を調節する手段とを設け、出
力トランジスタのコレクタ損失の変動によってバイアス
電流が変動するのを抑制するようにした電力増幅器を提
供するものである。
Purpose of the Invention Therefore, the present invention provides means for calculating the collector loss of the output 1·, /7 nostar from the output signal, and means for adjusting the bias voltage of the output stage according to the collector loss of the The present invention provides a power amplifier that suppresses variations in bias current due to variations in collector loss.

実施例の説明 第2図は、本発明の一実施例を示しだもので、第1図と
同一符号のものは同一のものを示しており、寸だ、6は
出力電圧まだは電流を検出して、出力トランジスタQl
、Q2のコレクタ損失を算出する回路、7はそのコレク
タ損失に応じてバイアス電圧を調節する回路である。
DESCRIPTION OF THE EMBODIMENT FIG. 2 shows an embodiment of the present invention. The same reference numerals as in FIG. Then, the output transistor Ql
, a circuit for calculating the collector loss of Q2, and 7 a circuit for adjusting the bias voltage according to the collector loss.

出力トランノスタQl、Q2に最適のバイアス電流を流
すだめに必要なバイアス電圧をVlとすると、Vlは出
力トランジスタのジャ7クション1品度TIにより、 Vl==VLa−(TL−’ra) ・Kまたたし、 
 Via・ノヤンクション温度がTaのとき必要なバイ
アス電圧、 Kl  定数、 で表わされるように変化する。
Let Vl be the bias voltage required to flow the optimum bias current to the output trannostars Ql and Q2, then Vl is determined by the output transistor's junction quality TI, as follows: Vl==VLa-(TL-'ra) ・K Again,
When the Via/noyanction temperature is Ta, the required bias voltage, Kl constant, changes as expressed by:

バイア供用トランジスタQ3のコレクタ、エミッタ間電
圧も同様に、 V2中V2a−(T2−Ta) ・Kまただし、  V
2・ツヤツク7ヨン温度が′r2のトキのコレクタ、エ
ミッタ間型 圧、 V2a  ノヤンクション温度がTa のときのコレクタ、エミ、り 間型圧、 Kl・定数、 出力トランジスタのコレクタ損失が最大になったときの
出力トランジスタおよびバイアス用トランノスタQ3の
それぞれのノヤンク7ヨン(品度をT l’ 、 T 
2’とすると、 T l’ −T 2’=Pc max、−θプこだし、
pc rTlaX、 −・出力トランジスタのコレクタ
損失の最火噴、 θ・・出力トランジスタからバイア ス用トランノスクまての熱4」( 抗(℃/W)、 となり、このどきバイアス用トランジスタQ3で与える
バイアス電圧が出力トランジスタQl 、Q2に必要な
最】箇バイアス電圧となるだめには、Vl’二v2’ ただし、■1′  出力トランノスタのノヤンクンヨン
温度がTl’のとき必要 なバイアス電圧、 V2’  ・・ぐイアス用トランノスタQ3のノヤンク
ション温度がT 2’ のときのQ3のコレクタ、エミ ッタ間電圧、 となるようにV2aを設定すればよいので、Kl=に2
二にであるなら、 V2a =V  l  a  −K  ・ (Tl’−
T2’)==V J a−に−Pc max、 θとな
るようにR1を調整ずil。ばよい。
Similarly, the voltage between the collector and emitter of the via transistor Q3 is V2a-(T2-Ta) in V2.
2. Collector-to-emitter die pressure when the junction temperature is 'r2, V2a Collector-to-emitter die pressure when the junction temperature is Ta, Kl/constant, The collector loss of the output transistor is at its maximum. When the output transistor and the bias transistor Q3 are different from each other (the quality is T l', T
2', T l' - T 2' = Pc max, -θ output,
pc rTlaX, - Maximum peak of the collector loss of the output transistor, θ... Heat from the output transistor to the bias transistor 4'' (resistance (℃/W)), and now the bias voltage given by the bias transistor Q3 To be the maximum bias voltage required for the output transistors Ql and Q2, Vl'2v2' However, ■1' When the temperature of the output transistor is Tl', the required bias voltage, V2'... V2a can be set so that the voltage between the collector and emitter of Q3 when the junction temperature of transistor Q3 is T 2', so Kl=2
2, then V2a = V l a - K ・ (Tl'-
R1 is not adjusted so that T2')==V J a- to -Pc max, θ. Bye.

この状9月で出力トランジスタQl 、Q2のコレクタ
損失が変化した場合、出力トラノノスタに必要となる・
ぐイアスミ圧V1と、バイアス用トランジスタQ:(で
与えられるバイアス電圧■2の差V (pc )は V (Pc) = Vl−V2 =に一θ(Pc max、 −Pc )たたし、 Pc
・出力トラノノスタのコレクタ損失、 となる。
If the collector losses of the output transistors Ql and Q2 change in this state, the required
The difference V (pc) between the bias voltage V1 and the bias voltage ■2 given by the bias transistor Q:
・The collector loss of the output trannostar is as follows.

以上のことから、コレクタ損失碧出回路6において出力
がコレクタ損失Pcに変換され、このpcに基づいてバ
イアス電圧調節回路7がV(pc)をりえることにより
、出力トランジスタQl 、Q2のコレクタ損失による
・ぐイアスミ流の変動を防IJ−することができる。
From the above, the output is converted to the collector loss Pc in the collector loss circuit 6, and the bias voltage adjustment circuit 7 changes V(pc) based on this pc, so that the collector loss of the output transistors Ql and Q2 is It is possible to prevent fluctuations in the Guiasmi flow due to IJ.

発明の効果 以−」二説明したように、本発明によれば、定常的な周
囲を7変の変化に対しても、1だ、出力トランジスタの
泡、檄な発熱に対しても、これに・11子して常に一定
の・ζイアスミ流を流すようにした電力増幅器を・提供
することができる。
Effects of the Invention As explained in Section 2, according to the present invention, it can withstand constant changes in the surroundings, bubbles in the output transistor, and excessive heat generation.・It is possible to provide a power amplifier in which a constant ζ-iasumi current is always supplied.

【図面の簡単な説明】[Brief explanation of drawings]

・貼1図は、従来の5EPP回路購成図、第2図は、本
発明の一実施例の回路構成図である。 Q、l、Q2・・出力トランジスタ、Q3 バイアス川
I・ランノスタ、R,l 、R,2・・・バイアス設定
抵抗器、6 ・出力信号から出力トランジスタのコレク
タ損失を算出する回路、7 コレクタ損失に応じてバイ
アス電圧を調節する回路。 第1図 1        3 2      4 第2図 3
- Figure 1 is a diagram of a conventional 5EPP circuit, and Figure 2 is a circuit configuration diagram of an embodiment of the present invention. Q, l, Q2... Output transistor, Q3 Bias river I/Lannostar, R, l, R,2... Bias setting resistor, 6 - Circuit that calculates the collector loss of the output transistor from the output signal, 7 Collector loss A circuit that adjusts the bias voltage according to the Figure 1 1 3 2 4 Figure 2 3

Claims (1)

【特許請求の範囲】[Claims] ツノグル・エンデッド・ゾッンユプル出力段を有する電
力増幅器において、出力電圧または電流全検出して出力
トランノスタのコレクタ損失を算出する手段と、算出し
たコレクタ損失に応じて前^己シングル・エンデッド・
プツシ−プル出力段ノバイアス電圧を調節する手段とを
備えてなり、前記出力トランノスタの自己発熱によるシ
ングル・エンデッド・ブツシュデル出力段のバイアス電
流のノ4れを補]Eするようにしたことを特徴とする電
力増幅器。
In a power amplifier having a single-ended output stage, there is a means for calculating the collector loss of the output transformer by detecting the entire output voltage or current, and a means for calculating the collector loss of the output transformer by detecting the entire output voltage or current, and a means for calculating the collector loss of the output transformer according to the calculated collector loss.
and means for adjusting the bias voltage of the pushpull output stage to compensate for the bias current of the single-ended pushpull output stage due to self-heating of the output transnoster. power amplifier.
JP57117832A 1982-07-08 1982-07-08 Power amplifier Pending JPS5910008A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57117832A JPS5910008A (en) 1982-07-08 1982-07-08 Power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57117832A JPS5910008A (en) 1982-07-08 1982-07-08 Power amplifier

Publications (1)

Publication Number Publication Date
JPS5910008A true JPS5910008A (en) 1984-01-19

Family

ID=14721350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57117832A Pending JPS5910008A (en) 1982-07-08 1982-07-08 Power amplifier

Country Status (1)

Country Link
JP (1) JPS5910008A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582319U (en) * 1992-04-15 1993-11-09 清太郎 大内 brush

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57185709A (en) * 1981-05-12 1982-11-16 Japan Radio Co Ltd Compensation circuit for operating point for transistor linear amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57185709A (en) * 1981-05-12 1982-11-16 Japan Radio Co Ltd Compensation circuit for operating point for transistor linear amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582319U (en) * 1992-04-15 1993-11-09 清太郎 大内 brush

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