JPS5899915U - gain control circuit - Google Patents
gain control circuitInfo
- Publication number
- JPS5899915U JPS5899915U JP19818681U JP19818681U JPS5899915U JP S5899915 U JPS5899915 U JP S5899915U JP 19818681 U JP19818681 U JP 19818681U JP 19818681 U JP19818681 U JP 19818681U JP S5899915 U JPS5899915 U JP S5899915U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- gain control
- control circuit
- collector
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の利得制御回路の一例を示す回路図、第2
図は同じく他の例を示す回路図、第3図、はこの考案に
係る利得制御回路の一実施例を示す回路図である。
Q2□〜Q3o・・・・・・トランジスタ、R21〜R
24・・・・・・抵抗、21.22・・・・・・入力端
子、24.25・・・・・・端子、26・・・・・・利
得制御信号発生回路、27. 30゜31・・・・・・
定電流回路、28.29・・・・・・出力端子。Figure 1 is a circuit diagram showing an example of a conventional gain control circuit;
FIG. 3 is a circuit diagram showing another example, and FIG. 3 is a circuit diagram showing an embodiment of the gain control circuit according to the invention. Q2□~Q3o...Transistor, R21~R
24...Resistor, 21.22...Input terminal, 24.25...Terminal, 26...Gain control signal generation circuit, 27. 30゜31・・・・・・
Constant current circuit, 28.29... Output terminal.
Claims (1)
第2のトランジスタと、この第1、第2のトランジスタ
のコレクターエミッタ電流路にそれぞれベースが接続さ
れる第3、第4−の叶うンジスタを有し差動増幅器構成
とされる負荷回路と、入出力端子のうちのいずれか一方
の端子が交流的に基準電位側に接続され他方の端子がそ
れぞれ前記第1、第2のトランジスタのコレクタ・エミ
ッタ電流路と前記第3、第4のトランジスタのベースと
の接続点に接続される第1、第2の定電圧回路と、利得
制御信号のレベルに応じて前記第1、第2の定電圧回路
を流れる直流電流レベルを制御する制御回路とを具備し
た利得制御回路。a first, each of which is supplied with a complementary input signal to the base;
a load circuit having a differential amplifier configuration, including a second transistor, and third and fourth transistors whose bases are connected to collector-emitter current paths of the first and second transistors, respectively; One of the output terminals is connected to the AC reference potential side, and the other terminal is connected to the collector-emitter current paths of the first and second transistors and the bases of the third and fourth transistors, respectively. and a control circuit that controls the level of direct current flowing through the first and second constant voltage circuits according to the level of the gain control signal. gain control circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19818681U JPS5899915U (en) | 1981-12-25 | 1981-12-25 | gain control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19818681U JPS5899915U (en) | 1981-12-25 | 1981-12-25 | gain control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5899915U true JPS5899915U (en) | 1983-07-07 |
Family
ID=30111379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19818681U Pending JPS5899915U (en) | 1981-12-25 | 1981-12-25 | gain control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5899915U (en) |
-
1981
- 1981-12-25 JP JP19818681U patent/JPS5899915U/en active Pending
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