JPS5899036A - Cmos gate circuit - Google Patents

Abstract

PURPOSE:To minimize the gate propagation delay time, by selecting the ratio of the width of transistors (TRs), in a CMOS gate circuit applied to an LSI of gate array system. CONSTITUTION:The proparation delay time of a gate can be minimized, by determining the threshold voltage of MOS TRs QP, QN and a power supply voltage VDD applied to the CMOS TR circuit, and selecting the ratio of the gate width of both the TRs QP, QN so that said ratios is equal to or close to n<1/2>.

Description

[Detailed description of the invention] The present invention relates to a CMOS gate circuit.

In particular, the present invention relates to a CMOS gate circuit applied to a gate array type LSI.

With the rapid progress of semiconductor technology and the application of semiconductor integrated circuits to various devices, there has been a strong demand for random logic LSIs that can be produced in small quantities with a short development period. Gate array type LSIs have been considered suitable for meeting such demands, and this type of LSI has already been put into practical use.

Also, in this type of integrated circuit, attempts have been made to develop a gate array element having a CMO3 structure, which has low power consumption and can have a large number of gates.

However, the CMOS gate array devices that have been developed so far cannot be said to have sufficient performance.

There was still room for improvement.

The present invention provides a CMOS transistor in which the gate propagation delay time can be minimized by selecting the gate width when designing a gate cell for a CMOS gate array. explain.

In Figure 1, a PMO8 transistor QP and an NMO8 transistor QN are connected between the power supply vDD and the ground.
MOS inverter circuit with one MOS transistor QP,
Input Vin is applied to the gate of QN, while output Vout is derived from both commonly connected drain terminals. A load capacitor CL is connected to the output Vout.

In the above CMOS inverter circuit, when the step-like signal Vin shown in Fig. 2(a) is applied to the input terminal as an input signal, the output is derived as a signal waveform Vout with a delay as shown in Fig. 2(b). Here, the fall time tf of the output signal Vout is the time for the output amplitude to fall from 90% to 10%, and the rise time t
r is defined as the time from 10% to 90%, and the propagation delay time j p d, which is the time required from the input signal being applied to the input terminal until the output signal appears at the output terminal, is defined as t
0 defined as pd=+(tf+tr) The above fall time t and rise time tr are given by the following equations.

However, β8. β1 is each NMO8) transistor QN,
PMO8) Beta value of transistor Qp.

Wear. Further, VTHN and vTHP are threshold voltages of NMO8) transistor QN and PMO8) transistor QP.

Now, CMO8) Power supply voltage v applied to the transistor circuit
Threshold voltage VTH of both DD9 MOS transistors
Once N and VTHP are determined, the above equations (1) and (2) can be written as 0C t, -f L/ (a) β
9t-ArCL/(4)rβ.

However, in the above AA, V V , V and f'
r DD' THN This is a constant determined by THP. At this time, the gate propagation delay time t
p d can be rewritten as follows, where PM
O8) Considering the beta value β of transistor QP as a function of gate width WP, β1=βPo·W4. It can be rewritten as Also, NMO8) Beta value β of transistor QN,
Since NMO8) transistors and PMO8) transistors are manufactured using a series of processes, NMO8)
) Using the gate width WN of the transistor and the coefficient βPo of the above PMOS transistor, it can be written as β9=nβPo−WN.In the CMOS transistor structure, the sum of the gate widths of both P and N MOS transistors WT=WP + WN is Once the cell shape is determined, it is uniquely determined, and the gate propagation delay times t and d expressed in the above equation (5) can be rewritten as 0 In the above equation (6), the gate propagation delay time t2. The relationship between the gate widths WP and WN that minimizes the following equation is obtained.

By setting the gate widths of PMO8) transistor Qp and NMOS transistor QN so that

The gate propagation delay times t, d can be minimized.

For example, if the threshold value of PMO8) transistor Qp and N, M.O8) transistor QN is set to VTHN=1vTHP1 transistor Qp and NMO8) transistor QN, the gate propagation delay time tdp will be minimized.

Generally, this is due to the difference in mobility between electrons and holes.

When the beta value β of the NMO8) transistor QN is rewritten, n is n>1. In this case, it is effective in terms of time extension.

In the conventional CMOS inverter circuit.

Although n) is 1, the pattern is designed as WN=WP or WN>WP, but this is due to L p
This is not desirable from the point of view of minimizing d.

Approximately 3% slower than the suitable pattern 0 In the above embodiment, an inverter was explained.

Even if it is a NOR, NAND or other composite gate.

If the final equivalent circuit is a gate circuit equivalent to an inverter, it can be applied in exactly the same way.

A circuit with excellent switching characteristics can be obtained, and particularly when applied to a CMOS gate array element, remarkable effects can be achieved.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a CMOS inverter, Figure 2 (a
) and (b) are waveform diagrams of input signals and output signals to the CMOS inverter circuit. QP: PMOS transistor, QN: NMO8) transistor + Vin: Input signal + Vout: Output signal Agent Patent attorney Aihiko Fuku

Claims (1)

[Claims] 1. In a CMOS gate circuit whose final electrical equivalent circuit can be expressed as an inverter, the beta positions β1. β8 is calculated using the respective gate widths WP and WN, β1=βpo・(Ar, A(is the power supply ■DD, PMO
Threshold voltage of S transistor V 7 Hp + and N
MO8) The gate propagation delay time t is equal to or close to the constant determined by the threshold voltage VTHN of the transistor.
, d is selected to minimize
S gate circuit.