JPS5897831A - Pattern formation - Google Patents
Pattern formationInfo
- Publication number
- JPS5897831A JPS5897831A JP19656781A JP19656781A JPS5897831A JP S5897831 A JPS5897831 A JP S5897831A JP 19656781 A JP19656781 A JP 19656781A JP 19656781 A JP19656781 A JP 19656781A JP S5897831 A JPS5897831 A JP S5897831A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- pattern
- etching
- oxide film
- frequency power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007261 regionalization Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 18
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 8
- 238000003682 fluorination reaction Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000011161 development Methods 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 229920003986 novolac Polymers 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 12
- 230000003685 thermal hair damage Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 102220058659 rs767802663 Human genes 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
発明や技術分野
本発明は、パターン形成方法に係わり、特にシリコン酸
化膜の反応性イオンエツチングに先立つレジストパター
ン形成方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern forming method, and more particularly to an improvement in a resist pattern forming method prior to reactive ion etching of a silicon oxide film.
発明の技術的背景とその間融点
近時、超LSI勢を構成する薄膜に微細パターンを正確
に蝕刻するものとして、反応性イオンエツチング法が用
いられている。この反応性イオンエツチング法は、第1
図に示す如く真空チェンバ1内に配置された一対の平行
平板電極2.3の高周波電力印加側の電極s上に試料4
を載置し、チェンバ1内に少なくとも1つのハロゲン原
子を分子内に含んだガスを導入すると共に、電極2.3
間に高周波電力を印加することにより放電プラズマを発
生せしめ、このプラズマを利用して試料4の被エツチン
グ部をエツチングする方法である。エツチング中の電極
2゜3間の直流電位は第一2図に示す如く電極2.3の
各電位ともプラズマ電位Pに対し卑となる。Technical Background of the Invention Near the melting point, reactive ion etching has been used to precisely etch fine patterns into thin films constituting VLSI devices. This reactive ion etching method
As shown in the figure, a sample 4 is placed on the high-frequency power application side electrode s of a pair of parallel plate electrodes 2.3 arranged in the vacuum chamber 1.
A gas containing at least one halogen atom in the molecule is introduced into the chamber 1, and an electrode 2.3 is placed on the chamber 1.
In this method, discharge plasma is generated by applying high-frequency power between the etching steps, and the portion of the sample 4 to be etched is etched using this plasma. During etching, the DC potential between the electrodes 2.3 becomes less noble with respect to the plasma potential P, as shown in FIG.
特に、馬脚電力が印加される備の電極3の電位(嘱極亀
位)Qとプラズマ電位Pとの差は数100 EV)にも
及ぶ。そして、この数100 (V)の直流電位差によ
り、プラズマ中の正イオンが電極(電極)3に向かって
加速され被エツチンク物を衝雅してエツチング反応が進
行する。反応性イオンエツチング法はこのイ、オン衝撃
を特徴とするため、特にプラズマエツチング法と区別さ
れている。In particular, the difference between the potential (electrode peak) Q of the electrode 3 to which the horse leg power is applied and the plasma potential P is as large as several 100 EV). Due to this DC potential difference of several hundred (V), positive ions in the plasma are accelerated toward the electrode (electrode) 3 and bombard the object to be etched, causing an etching reaction to proceed. The reactive ion etching method is distinguished from the plasma etching method because it is characterized by this i, ion bombardment.
ところで、反応性イオンエツチング法を用いてSi基板
上の”sjo、膜をエツチングする場合等、sio、の
エツチング速度に対してBiのエツチング速度を遅くす
る必要があり、CF、とHlとの混合ガス、CHF、
、 C,F、或いはC,F、等のガスが使用されている
。その結果、Siのエツチング速度は十分遅いものの、
aio、のエツチング速度も遅くなりスループットが低
くなる。sio。By the way, when etching a ``sjo'' film on a Si substrate using the reactive ion etching method, it is necessary to make the etching rate of Bi slower than the etching rate of sio. gas, CHF,
, C, F, or C, F, etc. are used. As a result, although the etching speed of Si is sufficiently slow,
The etching speed of aio is also slow and the throughput is low. sio.
のエツチング速度を速めるには印加高周波電力を大きく
すればよいが、高周波電力を増大させるとプラズマ電位
8よびガス温度が上昇するため、レジストが熱的損傷を
受はレジストパターンが荒れる等の問題を招く。この間
噛を解決するものとして、試料を電極板に吸着させ該電
極板を冷却することにより試料を冷却する方法が考えら
れるが、この場合上記吸着のため初静電チャック機構を
必要とし、エツチング装置構成の複雑化を招(。さらに
、直接レジストを冷却するのではないため、十分なる冷
却を行うことは困−であった。In order to increase the etching speed, it is possible to increase the applied high-frequency power, but as the high-frequency power increases, the plasma potential 8 and gas temperature rise, which may cause problems such as thermal damage to the resist and roughening of the resist pattern. invite A possible solution to this problem is to cool the sample by adsorbing the sample to an electrode plate and cooling the electrode plate. However, in this case, an initial electrostatic chuck mechanism is required for the adsorption, and an etching device is required. In addition, since the resist was not directly cooled, it was difficult to cool it sufficiently.
発明の目的
本発明の目的は、レジストの耐熱性向上をはかることに
より大きな高周波電力印加を可能とし、スループットの
向上および加工精度の向上をはかり得るパターン形成方
法を提供することにある。OBJECTS OF THE INVENTION An object of the present invention is to provide a pattern forming method that can improve the heat resistance of a resist, thereby making it possible to apply a large amount of high-frequency power, thereby improving throughput and processing accuracy.
発明の概要
本発明者等は、ポジ型レジストの熱的損傷に関して鋭意
研究を重ねた結果、レジストのポストベーキング温度が
高い程レジストは熱的損傷を受け―いと云う事実を見出
した。しかし、ポストベーキング温度がある一定温度(
通常140C程度)を越λるとレジスト自体が軟化し、
レジストプロファイルが悪化すると云う問題がある。そ
れゆえ、レジストを固めることを目的としてさらlこ本
発明者等が鋭意研究を重ねた結果、弗素ラジカルを用い
てレジスト表面を弗素化すると核表面が硬化し、160
E’)以上の温度でホストベーキングを行ってもレジス
トプロファイルが悪化しないと云う事実が判明した。SUMMARY OF THE INVENTION As a result of extensive research into thermal damage to positive resists, the present inventors have discovered the fact that the higher the post-baking temperature of the resist, the more likely the resist is to be thermally damaged. However, the post-baking temperature is a certain constant temperature (
If the temperature exceeds λ (usually about 140C), the resist itself will soften,
There is a problem that the resist profile deteriorates. Therefore, as a result of intensive research by the present inventors for the purpose of hardening the resist, it has been found that when the resist surface is fluorinated using fluorine radicals, the core surface hardens and the 160
It has been found that the resist profile does not deteriorate even if host baking is performed at a temperature of E') or higher.
本発明はこのような点に着目し、被加工膜上に塗布され
たレジストを所望パターンに露光したのち該レジストを
現偉してレジストパターンを形成し、次いで上記残った
レジストを弗素ラジカルで弗素化処理、例λばCF4と
H,との混合ガスプラズマで処理し、その後上記レジス
トを160 (C)以上の温度でポストベーキングし、
しかる肋ち反応性イオンエツチング法を用い上記レジス
トをマスクとして前記被加工膜を選択エツチングするよ
うにした方法である。The present invention has focused on these points, and after exposing a resist coated on a film to be processed to a desired pattern, the resist is exposed to form a resist pattern, and then the remaining resist is exposed to fluorine using fluorine radicals. oxidation treatment, for example, a mixed gas plasma of CF4 and H, and then post-baking the resist at a temperature of 160 (C) or more,
In this method, the film to be processed is selectively etched using the resist as a mask using the rib reactive ion etching method.
発明の効果
本発明によれば、レジストを弗素ラジカルで弗素化処理
したことにより、レジストを160(r)以上の温度で
ポストベーキングしてもレジストの軟化によるレジスト
プロファイルを貼止することができ、さらに上記レジス
トを用いることにより印加高周波電力を大きくしても該
レジストの熱的損傷を極めて小さくすることができる。Effects of the Invention According to the present invention, by fluorinating the resist with fluorine radicals, even if the resist is post-baked at a temperature of 160 (r) or more, it is possible to stick the resist profile due to the softening of the resist. Furthermore, by using the above-mentioned resist, thermal damage to the resist can be minimized even if the applied high-frequency power is increased.
したがって、誉加工膜のエツチング速度を速くすること
ができスループットの向上をはかり得る。さらに、エツ
チングli!lど受けるレジストの熱的損傷を少なくで
きるので、加工精屓の向上をはかり得る等の効果を奏す
る。Therefore, the etching speed of the processed film can be increased, and throughput can be improved. Furthermore, etching li! Since thermal damage to the resist can be reduced, processing precision can be improved.
発明の実施例
第3図(a) 、 (b)は本発明の一実施□例に係わ
るパターン形成工程−を示す断面■である。まず、第1
図(a)に示す如くP型B i III@ J J ヲ
1011198し、これらの基1111上に1000
(t?)の湿式酸化によりl〔μm〕の熱酸化膜(被加
工膜)12を編成し、続いて熱酸化JIIJJ上にノボ
ラック系ポジ型レジスト13(商品名OFPR−800
東京応化製)をスピンコードした。次に、1:1投影縛
光機を用いて上記レジストに所望パターンを露光したの
ち、アルカリ現俸液にて現像を90秒間行い、第3 [
!l (b)に示す如きレジストパターン14を形成し
た。Embodiment of the Invention FIGS. 3(a) and 3(b) are cross-sectional views illustrating a pattern forming process according to an embodiment of the present invention. First, the first
As shown in Figure (a), P-type B i III @ J J wo 1011198 and 1000
A thermal oxide film (film to be processed) 12 of 1 [μm] is formed by wet oxidation of (t?), and then a novolak positive resist 13 (product name OFPR-800) is formed on the thermal oxidation JIIJJ.
(manufactured by Tokyo Ohka) was spin coded. Next, a desired pattern was exposed on the resist using a 1:1 projection light exposure machine, and then development was performed for 90 seconds with an alkaline developer solution, and the third [
! A resist pattern 14 as shown in l(b) was formed.
かくして得られた試料を5枚づつ2組に分け、一方をケ
ミカルドライエツチング装置(曲品名CDE−11.徳
田製作所製)内に設置し、CF4flt、t120〔T
IJZ分〕、0.流量120(d/分〕、圧力0.2
(Torr )の条件下で弗素化処理を行った。次に、
これら5枚の試料をオーブンに入れ220 LC)で3
0分間ポストベーキングした。The samples obtained in this way were divided into two sets of 5 sheets each, and one was placed in a chemical dry etching device (product name: CDE-11, manufactured by Tokuda Seisakusho), and CF4flt, t120 [T
IJZ minute], 0. Flow rate 120 (d/min), pressure 0.2
The fluorination treatment was performed under conditions of (Torr). next,
Place these 5 samples in an oven and heat at 220 LC) for 3
Post-baked for 0 minutes.
また、残りの5枚の試料については、前記レジストパタ
ーン14のプロファイルを保持し得る上限のflAk−
140(t)で30分間のベーキング処理を行った。In addition, for the remaining five samples, the upper limit of flAk- that can maintain the profile of the resist pattern 14 is
Baking treatment was performed at 140 (t) for 30 minutes.
上述の2種類の方法で得られた試料を前記第1図に示し
た反応性イオンエツチング装置内の電極(下部電極)3
上に載置し、CF、流量20Ls#/分〕、H鴛流量3
0(d/分〕、圧力0.1 (Torr )の条件下で
、印加高周波電力を変えて熱酸化膜12のエツチング速
度を測?したところ第4図に示す結果が得られた。すな
わち、いずれの試料にあっても印加高周波電力の増大に
伴ってエツチング速度が速くなった。そしてこの場合、
通常の工程により作成された試料では、高周波電力60
0 [W)でレジスト13が損傷を受けしわが目立って
くるのが判明した。The samples obtained by the above two methods were placed at the electrode (lower electrode) 3 in the reactive ion etching apparatus shown in FIG.
Place it on top, CF, flow rate 20Ls#/min], H takashi flow rate 3
When the etching rate of the thermal oxide film 12 was measured under conditions of 0 (d/min) and a pressure of 0.1 (Torr) while changing the applied high-frequency power, the results shown in FIG. 4 were obtained. That is, For all samples, the etching rate increased as the applied high-frequency power increased.
For samples made by normal processes, high frequency power of 60
It was found that at 0 [W], the resist 13 was damaged and wrinkles became noticeable.
これに対し、前記弗素化処理および220 E’)のベ
ーキング処理を施された試料では、高周波電力1〔し〕
でもレジスト13は全く損傷を受けておらず、良好なエ
ツチングパターンを得ることができた。したがって、実
用し得る熱酸化膜(sio霊)12のエツチング速度を
1500(A/分分根程度ら3000[A/分〕程度才
で速めることが可能となった。On the other hand, in the sample subjected to the fluorination treatment and the baking treatment at 220 E'), the high frequency power was 1
However, the resist 13 was not damaged at all, and a good etching pattern could be obtained. Therefore, it has become possible to increase the etching rate of the practical thermal oxide film (SIO) 12 from about 1500 (A/min) to about 3000 [A/min].
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記弗素化処理におけるガス流量や圧力等
の条件、また前記ポストベーキング処理における温度条
件(160r以上)は、仕様番こ応じて適宜足めればよ
い。さらに、弗素化処理に使用したガスはCFsと0.
との混合ガスに限るものではなく、弗素ラジカルを生じ
せしめるt)のであればよい。また、前記レジストとし
てはポジ型の代りにネガ型にも適用することができる。Note that the present invention is not limited to the embodiments described above. For example, the conditions such as gas flow rate and pressure in the fluorination treatment, and the temperature conditions (160 r or more) in the post-baking treatment may be adjusted as appropriate depending on the specification number. Furthermore, the gas used for the fluorination treatment was CFs and 0.
It is not limited to a mixed gas with fluorine radicals, but any gas t) that generates fluorine radicals may be used. Furthermore, the resist may be of a negative type instead of a positive type.
さらに、弗素ラジカルを発生せしめるプラズマ装置は、
平行平板型に限らず円筒型でも可能である。また、被加
工膜としては#酸化#(SiOl)に限らず、各種のも
のに適用できるのも勿論のことである。その他、本発明
の要旨を逸脱しない範囲で、種々変形して実施すること
ができる。Furthermore, plasma equipment that generates fluorine radicals
It is possible to use not only a parallel plate type but also a cylindrical type. Furthermore, it goes without saying that the film to be processed is not limited to #oxidized #(SiOl), but can be applied to various other films. In addition, various modifications can be made without departing from the gist of the present invention.
第1図は反応性イオンエツチング装置の概略構成を示す
模式図、第2図は上記装置内での直R11L位分布を示
す模式図、第3図(Jl) 、 (b)は本発明の一実
施例に係わるパターン形成工程を示す断面図、第4図は
印加高周波電力とエツチング速度との関・1)を示す特
性図である。
1・・・真空チェンバ、2,3・・・電極、4・・・試
料、5・・・高局波電漁、6・・・マツチングボックス
、11・・・81基板、12・・・熱酸化膜(被加工@
)、13・・・レジスト、14・・・レジストパターン
。
出願人代理人 弁理士 鈴 江 武 彦第1図
第2図
第3図
高川儂飽力□□□〕FIG. 1 is a schematic diagram showing the general configuration of a reactive ion etching device, FIG. 2 is a schematic diagram showing the direct R11L position distribution in the device, and FIGS. FIG. 4 is a cross-sectional view showing the pattern forming process according to the embodiment, and a characteristic diagram showing the relationship between the applied high frequency power and the etching rate (1). 1... Vacuum chamber, 2, 3... Electrode, 4... Sample, 5... High frequency electromagnetic fishing, 6... Matching box, 11... 81 substrate, 12... Thermal oxide film (processed @
), 13... resist, 14... resist pattern. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Takagawa Mekuryoku□□□〕
Claims (1)
ーンに■光したのち該レジストを現偉してレジストパタ
ーンを形成し、次いで弗素ラジカルにより上記レジスト
表面を弗素化処理し、次いで上記レジストを160 (
C)以上の温度でポストベーキングし、しかるのち反応
性イオンエツチング法を用い上記レジストをマスクとし
て前記被加工膜を選択エツチングすることを%惨とする
パターン形成方法。 (2) 前記被〃ロエ膜として、8tO,膜を用いた
ことを特徴とする特1Ffli!求の範囲第1項記載の
パターン形成方法。 (3)前記弗素化処理する手段として、前記レジストを
CF、と0意との混合ガスプラズマで処理することを特
徴とする%FF請求の範囲第1項6ピ載のパターン形成
方法。[Claims] <11 After exposing a resist coated on a film to be processed to a desired pattern, the resist is exposed to form a resist pattern, and then the resist surface is fluorinated with fluorine radicals. , then apply the above resist to 160 (
C) A pattern forming method that eliminates post-baking at a temperature above and then selectively etching the film to be processed using the resist as a mask using a reactive ion etching method. (2) Special feature 1Ffli!, characterized in that an 8tO film is used as the Roe coating film. The pattern forming method according to item 1. (3) The pattern forming method according to claim 1, item 6, wherein, as the means for the fluorination treatment, the resist is treated with a mixed gas plasma of CF and O2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19656781A JPS5897831A (en) | 1981-12-07 | 1981-12-07 | Pattern formation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19656781A JPS5897831A (en) | 1981-12-07 | 1981-12-07 | Pattern formation |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5897831A true JPS5897831A (en) | 1983-06-10 |
Family
ID=16359879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19656781A Pending JPS5897831A (en) | 1981-12-07 | 1981-12-07 | Pattern formation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5897831A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6083332A (en) * | 1983-10-12 | 1985-05-11 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Method of forming polymer pattern |
JPS6237932A (en) * | 1985-08-13 | 1987-02-18 | Matsushita Electronics Corp | Resist-pattern forming method |
-
1981
- 1981-12-07 JP JP19656781A patent/JPS5897831A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6083332A (en) * | 1983-10-12 | 1985-05-11 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Method of forming polymer pattern |
JPS6237932A (en) * | 1985-08-13 | 1987-02-18 | Matsushita Electronics Corp | Resist-pattern forming method |
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