JPS589639B2 - Delay amount correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a delay amount correction method for correcting the delay in transmission between frames due to the distance between frames in a digital exchange in which a plurality of large-scale switches are mounted.

FIG. 1 is a block diagram of a space switch section in a digital exchange, and shows an example of an Nn×Nn square lattice.

That is, the input highway ■. There are Nn output highways Oo-ONn-1 compared to Nn output highways Oo-ONn-1.

If this N n × N n matrix is large, it will be divided into N pieces and each piece will be mounted on a separate rack.

Incidentally, a configuration diagram of the cross point is shown in FIG. 1b.

Also, input highway I (J-1).

It is assumed that n books of ~I J n-1 are stored in the J-th rack and distributed from the J-th rack to other racks.

That is, FIG. 1C shows a diagram in which the input highway is distributed over a plurality of racks, and as shown in FIG.

- n pieces of In1 are receiving circuits RFC housed in the first rack.
are stored in the first rack via It is accommodated in the J-th rack via the receiving circuit REC housed in the n-th rack, and is sequentially distributed from the rack closest to the J rack to the other racks.

Next, input the operating principle of the space switch section using Figure 2, which is a detailed partial diagram of the space switch section.

In the case of four lines in ~■3, the output highway Oo will be explained.

The holding memory HM is constantly and periodically read out in synchronization with the time slots of the time division exchange.

The read control data is held in register R and expanded by expansion circuit EXP to control each gate GO to G3.

For example, it is assumed that control data "2" is written at address i in the holding memory HM.

At time slot i, address i of holding memory HM is read out and sent to gate G through register R1 expansion circuit EXP.
2 is opened, and the data from the input highway ■2 comes out to the output highway Oo.

That is, in time slot i, the input data of input highway 2 is output to output highway O.

It means that you have been switched off. As shown in FIG. 1, the space switch is constructed by connecting the same number of such circuits as the number of output highways.

If it is large-scale as shown in Figure 1, multiple racks (N
It will be distributed and implemented on multiple platforms.

Therefore, the arrival of input data for each rack will be inconsistent due to the difference in transmission time between the racks.

FIG. 3 shows a time chart of the input highway in the conventional method, and is a time chart of input data at the J rack.

Highway I (J-1) is on the J rack.

~■Jn-, is accommodated, so for example, considering the crosspoint connected to the output highway 0 (J-1) n of the J frame, the input highway I (J
, )n+q (q is O~(ni)) will naturally be inputted first.

Now, depending on the input highway distribution method, the input highway ■.

It is assumed that the input data from .

Highway ■. The time difference Td seconds between the input data from and from I (J-1) n-1-q is the maximum value of the variation when the input arrives.

The time difference Td of input data mainly depends on the delay due to inter-frame transmission.

If Tp seconds is the width of the time slot, then as can be seen from FIG. 3, data from all the input highways are present during the hatched time period TG=Tp-Td seconds.

Therefore, data switching is possible only during these TG seconds.

When the switching time in the rack is Ts seconds, the operating conditions are 'rG='rp-'rct≧Ts becomes.

The maximum allowable value of the delay time Td is determined from the time slot width Tp and the switch time Ts.

Since the delay time Td depends on the distance between the frames, the maximum distance between the frames is restricted.

Thus, in conventional approaches it is not possible to make the system larger than a certain point.

The present invention corrects the amount of delay between racks in order to eliminate these drawbacks, and provides a delay amount correction method that can eliminate restrictions on the distance between racks for the maximum scale of the system. .

That is, the space division switch section of the digital exchange is distributed and mounted on multiple racks, and the input highway is distributed among the multiple racks to be accommodated and distributed to other racks. A clock distribution circuit and a frame pulse distribution circuit are installed, and a reference counter that counts the clock distributed from the clock distribution circuit and is initialized by the frame pulse distributed from the frame distribution circuit is installed on each rack. Initial settings using frame pulses are performed by setting the transmission time between a specific rack and the relevant rack by a value standardized by a clock, synchronizing the reference counters of multiple racks, and The supply of input data to the internal switches is delayed by the maximum interframe transfer delay time using a delay circuit.
The input data is supplied to the switches of other racks to which the input highway is distributed by distributing distributed human data delayed by a time equal to the difference between the maximum inter-frame transfer delay time and the inter-frame transfer delay time. This is a delay amount correction method.

FIG. 4 is a time chart illustrating the standardization of interframe transfer delay time in the present invention.

A case will be described in which the J-th rack receives input data sent from the first rack (the input highway is stored in the first rack and distributed to other racks).

IO OOT is the data output from the first rack, ■JUN
is the data input to the J rack.

When the input data sent from rack ① at clock CL 0 can be received by rack J at clock 1 (in the range shown by the hatch in Figure 4, the rising edge of the input from rack J is (i-1)).
range of rising edge of clock and rising edge of i clock), Part ■
The delay between the frame and the J frame is normalized by the clock CL and becomes the i clock delay.

In this way, the interframe transfer delay time is standardized by the clock CL, but the maximum interframe delay (for example, the first and Nth
The following explanation will be given assuming that the clock is k clocks.

FIG. 5 shows a circuit diagram for explaining delay amount correction according to the present invention.

For example, input highway Iq (
In order to supply the input data from 0 to (n-1)) to the switch SW in the frame, a delay circuit DLYk delays the maximum inter-frame transfer delay time k clock, and the inter-frame transfer delay time is set to, for example, i clock. A delay circuit DLYt is used to supply the signal to the switch SW of another rack, such as the J rack, at a delay time of t = k −
It is delayed by i clock and used as a distribution input.

Therefore, the input highway I (J-1) of the Jth rack receives the supply from the No.1 rack.

+, is delayed by t + i = k clocks.

By performing this delay correction for all racks and between racks, the highway data supplied to the switch will be corrected regardless of whether it is from the highway accommodated in the own rack or from the highway distributed. All signals are delayed by an equal delay amount k clocks until they reach the switch, and switching becomes possible.

Note that Im in FIG. 5 is an input highway that is delayed from another rack and is supplied to the switch of the first rack.

In order to perform the above-described operations normally, the reference counter COUNT (installed on each rack) that counts the time slots that are the basis of the operation must operate in synchronization.

For this purpose, it is necessary to distribute the clock CL and frame pulse FP from a specific one of the plurality of racks (for example, the No. 1 rack) to each of the other racks.

The distribution circuit is shown in FIG.

In the specific rack, for example, the Pth frame pulse is set in the reference counter COUNT.

For other racks (for example, rack J), if the delay time from the specific rack (frame ①) is S, then 'p+s'' is initialized with a frame pulse.

The reference counter COUNT operates synchronously on all racks, and allows accurate various timings (e.g., frame position pulses, time slot information, etc.) to be generated from the reference counter COUNT to perform the above-described switching operations across the racks. can.

In addition, in FIG. 6, the delay circuit CL inserted into the J rack
DLY is for aligning the clock phases in each rack.

As described above, the present invention has the advantage that even if input data is delayed between the frames, there is no restriction in terms of the distance between the frames relative to the maximum scale of the system.

This is effective for digital exchanges in which the space switch sections are distributed over multiple racks.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of the space switch section in a digital exchange, Fig. 2 is a partial detailed view of the space switch section, Fig. 3 is a time chart of the input highway in the conventional system, and Fig. 4 is the interframe transfer delay in the present invention. FIG. 5 is a time chart for explaining time normalization, FIG. 5 is a circuit diagram for explaining delay amount correction according to the present invention, and FIG. 6 is a clock and frame pulse distribution circuit diagram according to the present invention. DLYk, DLYt, CLDLY...Delay circuit, COUNT...Reference counter.

Claims (1)

[Claims] 1. The space division switch section of the digital exchange is installed in a distributed manner on multiple racks, and the input highway is distributed among the multiple racks to be accommodated and distributed to other racks. A clock distribution circuit and a frame pulse distribution circuit are installed, and a reference counter is installed on each rack to count the clock distributed from the clock distribution circuit and initialize with the frame pulse distributed from the frame distribution circuit. Initial settings using frame pulses are performed by advancing the set value by a value standardized by the clock for the inter-frame transmission time between a specific rack and the relevant rack, synchronizing the reference counters on multiple racks, and The supply of input data to the switch is delayed by the maximum inter-frame transfer delay time, and the supply of input data to the switch of the other rack to which the input highway is distributed is delayed by the maximum inter-frame transfer delay time and the relevant frame. A delay amount correction method characterized by distributing distribution input data that is delayed by a time equal to the difference from the inter-transfer delay time.