JPS5896343A - Data skew buffer circuit - Google Patents

Abstract

PURPOSE:To shorten the passing time of a buffer circuit and to improve a data transfer speed, by forming a bypass for transfer from the starting data buffer to the ending data buffer of the buffer circuit when the buffer circuit is completely idle. CONSTITUTION:Data is sent from a precedent buffer to a buffer 4 and stored therein and when the data is stored in a trailing buffer, a signal 14 is generated. A signal 15 shows one of buffers 5-7 is full at the time when the signal 14 is generated. Namely, when the signal 15 is positive, an AND gate 11 ANDs the signals 14 and 15 and generates a truth output 16 to store output data 10 in the buffer 5. Then, the signal 15 gets negative when the buffers 5-7 are all idle, and an inverter 12 generates a real output 18; and an AND gate 13 ANDs the signals 14 and 18 to generate a real outut 17, thereby storing the output data 10 in the buffer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a data skinny buffer in a data transfer path of a conbeater system.

The data skinny buffer is for equalizing data transfer between each circuit (between each device) located on a data transfer path. FIG. 1 shows a conventional example. Although it is stipulated that data be transferred at a constant speed between each circuit, the transfer may be delayed due to some reason in the upper transmitting circuit 1. At that time, the data that was preempted in the data skinny buffer 2 is sent to the lower receiving circuit 3, thereby smoothing the transfer. However, the conventional circuit has the following problems. If data arrives from 1 when all stages of data buffers, i.e. 4.5.6.7, are empty, the data will flow from 4 to 5.5 to 6.6 to 7, and from 7 to 3. It takes a long time because the data falls between each stage of the buffer one after another. For example, if the delay time of each stage is tI, then in the example of FIG. 1, the time from 1 to the time when the sent data enters 4 and reaches 7 is 5t+゛). Generally, when there are n stages, from entering the input stage until reaching the final stage (n
-1) It takes t.

An object of the present invention is to bypass a part of the data skinny buffer when all the stages are empty, thereby shortening the time for passing through the data skinny buffer and transferring data quickly.

Data skinny buffers are necessary to smooth data transfer, but conversely, even when all stages of the buffer are empty, data always flows through all stages, so there is a risk that it will become a useless and long buffer.This problem has been solved. Therefore, the gist of the present invention is to bypass a part of the data buffer when all stages are empty.

FIG. 2 shows an embodiment of the present invention. data ski 972
If all stages are empty in 77 circuit 2, host device 1
The data 8 sent from the output stage 4 first enters 4, but then bypasses 5.6 without falling to 5 and is dropped to the final output stage 7. Therefore, in this example, the time from entering 4 to dropping to 7 is tl, which is 2t+ faster than the conventional example shown above.

Next, FIG. 3 shows an embodiment of the bypass circuit of the present invention. 10 indicates the output data of 4, and also serves as the input of 5 and 7. The signal 16 is a trigger signal to input the output data 10 to 5, and the ib signal 17 is a trigger signal to input the output data 10 to 7. 14 is a signal generated when the higher-order data is sent to 4 and stored, and the data is transferred to the next stage. Signal 15 is a signal indicating that the times at which signal 14 occurs vary. Therefore, when the signal 15 is positive, AND gate 11 performs an AND operation on 14 and 15, output 16 of 11 is not true, and output data 10 is stored at 5. Also, when all of 5.6.7 are empty, 15 is not false, and the output 18 of 12° is true by the inverter 12. AND of IA and 18 is done by the side gate 15, and the output 17 of 15 is true. The output data 10 is stored in 7.

The present invention improves the performance of the data ski puffer. In other words, when all n stages in an n-stage buffer are empty,
Data reaches the final output stage of the data ski buffer faster by (n-1) than in the conventional circuit. Generally, the number of stages of a data ski buffer is set so that all stages will not become empty, but if a situation where all stages become empty occurs, it is required to transfer data as quickly as possible. The present invention is effective.

[Brief explanation of the drawing]

Figure 1 shows a conventional data keypad.
3 is a diagram showing a data key buffer according to the present invention, and FIG. 3 is a diagram showing an example of a data buffer switching control circuit. 1... Upper transmitting circuit 2... Data ski buffer 3... Lower receiving circuit 4.5.6.7... Data buffers at each stage forming the data ski buffer 11.15...・AND gate 12...Inverter 14...Input 15 of AND gates 11 and 13...-Input of AND gate 11 and I/NO (-Input 16 of gate 12...Data at output of AND gate 11) Trigger signal 17 for receiving the output 10 into the data buffer 5...Trigger signal 1B for receiving the data output 10 into the data buffer 7 with the output of the AND gate 13...Input of the AND gate 15 with the output signal of the inverter 12 Representative Patent Attorney Susuki 1) Toshiyuki. ρ1=, Le Sai 1 Hi Sai 2 Yen

Claims (1)

[Claims] In a data buffer circuit consisting of multi-stage data buffers and configured such that the data in the previous stage data buffer is sequentially transferred to the next stage (7) data buffer, when all the buffer circuits are in an empty state. A demescue 922 buffer circuit, characterized in that it comprises means for bypassing and transferring data from the most advanced data buffer of the buffer circuit to the final stage data buffer.