JP2002252628A - Packet output adjustment device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly increase timing margin for scheduling and strike a balance between the speeding up of line speed and increase of switch size. SOLUTION: A counter is provided for each input line and the counter value is increased by the same number to keep fairness. The number to be increased is set to an appropriate value for the packet length at the point of time. A plurality of stages of these packet scheduling circuits are provided and the adjustment is made dispersedly and in pipeline arrangement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for an apparatus for arbitrating and outputting packets arriving from a plurality of input lines to output lines. In particular, it is suitable for use in arbitration output of packets of variable length, and is suitable for use in a device that requires both high output line speed and a large number of queues. The present invention relates to an improvement of Japanese Patent Application No. 2000-026959 (not disclosed at the time of filing the present application, hereinafter referred to as a prior application).

[0002]

2. Description of the Related Art FIG.
This will be described with reference to FIG. FIG. 3 is a block diagram of the packet scheduling circuit of the prior application. This device is a one-stage FI
It includes buffers 100 to 107, which are FO type buffers, and a packet output arbitration circuit 120 for arbitrating the packet outputs of the buffers 100 to 107. When transmitting a packet, the packet output arbitration circuit 120 calculates, for each buffer, a difference obtained by subtracting a counter value provided for each packet from the queue length of the first packet held in each of the buffers 100 to 107. The packet is transmitted from the buffer i (i is any of 100 to 107) having the minimum value. Then, the counter values of the buffers other than the buffer selected for packet transmission are reset to 0, and at the same time, the minimum value of the difference (hereinafter, referred to as
The counter value is updated by adding “granularity”. In the buffer i selected for packet transmission, cells are sequentially transmitted every cell time until the last cell constituting the packet is transmitted from the buffer i to the output line.

[0003] In this method, the granularity to be added to the counter is changed every time a packet is transmitted. Therefore, compared with the DRR (Deficit Round-Robin) method proposed for a long time,
There is an advantage that the average packet delay can be kept small.

[0004]

However, the packet scheduling circuit of the prior application has a problem that it is difficult to deal with scalability, that is, an increase in the number of buffers. This will be described.

In the packet scheduling circuit of the prior application, when the number of buffers is 2 ^N and the tournament method is used to determine the minimum value of the difference, the minimum value (granularity) is determined by N minimum comparison operations. Required.

For this reason, when the packet scheduling circuit of the prior application is applied to a switch having a large number of ports, the number of magnitude comparison operations for judging the minimum value increases, and a predetermined period of time increases as the output line speeds up. A problem arises in that the arbitration scheduling of the packet output does not end within the network.

In particular, in a situation where short packets, for example, short packets composed of one cell, are consecutive, it is necessary to complete the scheduling of the packet arbitration output within one cell time. As the scale increases, the timing constraints of packet output arbitration become even more severe.

Assuming now that the line speed is C [bit / sec] and the minimum packet size is L [bit], the scheduling time for the minimum packet is L / C [sec].
Becomes For example, assuming a line speed of C = 10 [Gbit / s] corresponding to OC-192c and a minimum packet size of 64 bytes corresponding to one ATM cell, the scheduling time for the minimum packet is only 51.2. [Nsec], and when the number of buffers is 2 ^N as described above, it is necessary to complete N magnitude comparison operations within this time.

For this reason, when the switch scale is increased and the number of buffers is increased, the comparison processing of the difference between the head queue length of the buffer and the counter value required for determining the granularity cannot be performed in time. As described above, in the conventional packet output arbitration device, it is difficult to achieve both an increase in the line speed and an increase in the number of ports, that is, the scale of the switch.

The present invention has been made in view of such a background, and a packet output capable of greatly increasing a timing margin of scheduling and capable of coping with both an increase in line speed and an increase in switch size. It is an object to provide an arbitration device. SUMMARY OF THE INVENTION It is an object of the present invention to provide a packet output arbitration device that can suppress cell loss even when input traffic is biased.

[0011]

The present invention is characterized in that arbitration is performed in a distributed and pipelined manner by providing a plurality of buffers instead of performing arbitration intensively.

The number of routes, that is, the number of buffers is 2 ⁿ . First, the first stage F for holding the arrival packet
Divide the IFO buffer into 2 ^m1 groups. As a result, the number of buffers in each divided group is 2 ^n-m1 .

[0013] buffer output in each group is calculated the prior application as well as the minimum granularity for specifying the output buffer by the number of buffers is decreased from 2 ⁿ to 2 ^n-m1, the timing of the packet output mediation Is greatly alleviated. In this case, the first-stage packet scheduling circuit performs packet transfer at almost the same speed as the output line speed so that the buffer can be prevented from being full and cell loss can be suppressed even when the input traffic is biased. It shall be sent to the FIFO buffer of the stage.

That is, while the packet scheduling circuit of the prior application required n times of magnitude comparison operations,
In the present invention, the number of magnitude comparison operations at the time of packet arbitration output of the first-stage FIFO buffer is reduced to nm1.

Next, 2 ^m1 first-stage packet scheduling circuits arbitrate and output packets to the second-stage FIFO buffer. In the FIFO buffer of the second stage, as in the first stage, by dividing the buffer and performing packet output arbitration independently for each group, the scheduling time can be greatly reduced.

Similarly, the final stage packet scheduler arbitrates and outputs packets to the output line. By thus configuring the buffer and the packet schedule circuit in a multi-stage configuration, it is possible to process the transmission of the packet to the output line in a parallel and pipeline manner, and it is possible to greatly reduce the scheduling time. Therefore, it is possible to cope with both the increase in the line speed and the increase in the switch scale.

The reason why the packet read speed of the packet schedule circuit can be set to substantially the same speed as the output line speed is that the packet output arbitration apparatus of the present invention can be operated at a high speed, thereby biasing the input traffic. Even if the error occurs, the buffer can be prevented from being full, and the cell loss can be suppressed.

That is, the present invention relates to a packet output arbitration apparatus provided with output arbitration means for outputting packets arriving from a plurality of input lines to one output line. The arbitration means includes a plurality of packet schedule circuits connected in cascade in multiple stages, and one of the packet schedule circuits is configured to read a plurality of packets respectively read from the plurality of input lines or the plurality of routes of the preceding packet schedule circuit. Each of the plurality of buffers is provided with a plurality of buffers. The plurality of buffers are classified into a plurality of groups including two or more buffers. Each of the plurality of buffers has a counter with an initial value of zero, and a first packet length of the buffer. Means for respectively calculating a difference between the counter value and each of the plurality of buffers; Means for selecting a buffer whose calculation result of the means for calculating the minimum value is obtained, means for adding the minimum value to counter values of buffers other than the buffer whose calculation result is the minimum value, and means for calculating the minimum value of the calculation result. Means for reading the first packet from a buffer serving as a value to the output line or a subsequent packet schedule circuit;
Means for resetting the counter value of the buffer from which the first packet has been read to zero.

It is desirable that the packet read speed of the packet schedule circuit is set to be substantially equal to the output line speed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a packet output arbitration apparatus according to an embodiment of the present invention will be described with reference to FIGS. Figure 1
FIG. 1 is a block diagram of a packet output arbitration device according to a first embodiment of the present invention. FIG. 2 is a block diagram of a packet output arbitration apparatus according to a second embodiment of the present invention.

The present invention relates to a packet output arbitration apparatus provided with output arbitration means for outputting packets arriving from a plurality of input lines to one output line. As shown in FIG. 2, the output arbitration means includes a plurality of packet schedule circuits connected in cascade in multiple stages. One of the packet schedule circuits is described in the example of the second stage packet schedule circuit in FIG. , Four buffers 70 to 73 for respectively storing a plurality of packets respectively read from four routes of the packet schedule circuit, and the four buffers 70 to 73 are provided with two buffers 70 and 7.
Divided into two groups, including 1, 72 and 73,
Counters 80 to 83 provided in the four buffers 70 to 73, each having an initial value of zero;
The difference between the length of the first packet 73 and the value of the counters 80 to 83 is calculated for each of the four buffers 70 to 73, the buffer having the minimum calculation result is selected, and the minimum value is calculated by the above calculation. The results are respectively added to the counter values of the buffers other than the buffer having the minimum value, the first packet is read out from the buffer having the minimum calculation result to the packet scheduling circuit at the subsequent stage, and the counter of the buffer from which the first packet has been read is read out. It is provided with packet output arbitration circuits 90 and 91 for resetting the value to zero.

The packet read speed of the packet schedule circuit is set substantially equal to the output line speed.

Hereinafter, embodiments of the present invention will be described in more detail.

(First Embodiment) A packet output arbitration apparatus according to a first embodiment of the present invention will be described with reference to FIG. In this example, a packet arrives from eight routes, and the arriving packet is buffer 1 which is eight FIFO buffers of the first stage.
It is held at 0-17. First stage buffers 10-17
Is divided into two groups. Each group includes a first group of buffers 10 to 13 and a buffer 14.
It is divided into the second group of ~ 17. Then, in each group, the output arbitration of the packet is independently performed for the four buffer outputs. Each of the buffers 10 to 17 has counters 20 to 27, and the value is updated each time an output packet is selected.

The case where a packet is selectively output from the first group will be described as an example. As the buffer to which the packet is output, the head packet length L in the buffer
Difference di = Li− between i [cell] and counter value ci
The buffer with the smallest ci is selected. Here, i is a port number, i = 0, 1, 2, 3 in the first group, and i = 4, 5, 6, 7 in the second group. When the buffer to output the packet is selected, the counter value is updated next. The counter value of the buffer to which the packet is sent is reset to zero. The counters of the other buffers not selected are min
Add the value of {0 ≦ i ≦ 3} di. Once a transmission packet is selected, cells are output every cell time until reaching the last cell of the packet.

Here, the effect of relaxing the scheduling time of packet output arbitration by dividing the buffer into groups will be considered. In this example, the output timing of the cell is set to be almost the same as the output line speed so that even if the input traffic is biased, the buffer is not full and the cell loss can be suppressed. As described above, it is necessary to calculate the difference between the head packet length in the buffer and the counter value for each buffer, and determine the minimum value of the difference value, that is, the granularity.

In the conventional device, in order to perform the packet output arbitration of eight buffers, a total of 1
og ₂ 8 = 3 times although the magnitude comparison was necessary, because the number of buffers in each group in the present invention the first embodiment are reduced to four, the magnitude comparison operations required difference value log
₂ 4 = reduced to 2 times. Therefore, the scheduling margin within one cell time can be greatly increased. The packets output from the two groups including the buffers 10 to 17 in the first stage are held in the two buffers 18 and 19 in the second stage.

The packet output from the buffers 18 and 19 in the second stage is determined from the minimum value of the length of the first packet in the buffer and the difference between the counter values, as in the first stage. In the second stage, since the number of buffers is two, only one comparison operation of the difference value required for determining the granularity is required, so that the scheduling timing margin is further increased compared to the first stage packet output arbitration. I have.

(Second Embodiment) A packet output arbitration apparatus according to a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, as in the first embodiment, packets arrive from eight routes, and the arriving packets are held in buffers 40 to 47, which are eight FIFO buffers of the first stage. The first-stage buffers 40 to 47 are classified into four groups, each two buffers. In each group, the minimum value of the difference between the leading packet length held in the buffer and the counter value is determined for two buffers to determine the granularity, and the buffer for packet output is determined. Packets output from the four groups are held in buffers 70 to 73, which are FIFO buffers of the second stage.

The buffers 70 to 73 in the second stage are divided into two groups of two. In each group, arbitration of packet output is performed independently, and packets output from each group are held in two buffers 92 and 93 at the third stage. The third-stage buffers 92 and 93 also perform output arbitration on the two buffers 92 and 93 and transmit packets to the output line. Since the packet output arbitration in the first, second, and third stages relates to two buffers, the scheduling time as a whole is further reduced as compared with the first embodiment.

[0031]

As described above, according to the present invention,
The FIFO type buffer has a multi-stage configuration in a pipeline manner,
In each stage, buffers are grouped and managed, and packet output arbitration is performed in a distributed manner, so that the scheduling timing margin can be greatly increased. As a result, it is possible to achieve both an increase in the line speed and an increase in the scale of the switch, which are difficult to realize with the conventional packet output arbitration device. In addition, even when input traffic is biased, cell loss can be suppressed.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional packet output arbitration device.

[Explanation of symbols]

10-19, 40-47, 70-73, 92, 93, 1
00-107 buffer 20-29, 50-57, 80-83, 94, 95, 1
10-117 Arbitration counter 30-32, 60-63, 90, 91, 96, 120
Packet output arbitration circuit

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naoaki Yamanaka 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term (reference) in Nippon Telegraph and Telephone Corporation 5K030 GA01 GA13 HA08 JA01 JA02 JA11 KA03 KX12 KX21 LE03 LE06 MA13 MB11 5K034 AA01 AA05 EE11 FF10 FF11 HH23 HH37 HH50 JJ19

Claims (2)

[Claims] 1. A packet output arbitration device comprising output arbitration means for outputting packets arriving from a plurality of input lines to one output line, wherein said output arbitration means includes a plurality of packet schedule circuits connected in cascade and in multiple stages. The one packet schedule circuit includes a plurality of buffers for respectively storing a plurality of packets read from the plurality of input lines or the plurality of routes of the preceding-stage packet schedule circuit, respectively. Classified into a plurality of groups including two or more buffers, a counter provided in each of the plurality of buffers and having an initial value of zero, and a difference between a leading packet length of the buffer and the counter value is calculated for each of the plurality of buffers. Means for calculating each, and a buffer for which the calculation result of the means for calculating becomes the minimum value. Means for selecting a key, a means for adding the minimum value to the counter value of a buffer other than the buffer having the minimum calculation result, and a head packet from the buffer having the minimum calculation result for the output line. Alternatively, a packet output arbitration device comprising: means for reading out to a packet scheduling circuit at a subsequent stage; and means for resetting a counter value of a buffer from which a leading packet has been read out to zero. 2. The packet output arbitration apparatus according to claim 1, wherein a packet read speed of said packet schedule circuit is set substantially equal to said output line speed.