JPS589612B2 - counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to N delay circuits (shift registers, flip-flops, etc.) used in frequency dividers of electronic watches, clock pulse generators of digital electronic equipment, various timing pulse generation circuits, etc. ) are connected in sequence and the output of the final stage is inverted and supplied to the input of the first stage.

Conventionally, a delay circuit that outputs an input state applied to an input terminal as an output state to an output terminal after a certain period of time according to a clock pulse is connected in cascade in N stages with the same clock pulse source as shown in Figure 1, and a final stage (N stage). 2) If the output is inverted and used as the input for the first stage, this circuit generally becomes (2×
N) It is known that it becomes a base counter.

In this counter, the state (initial state) of each delay circuit when the power is turned on is indefinite and cannot be predicted, but when clock pulses are supplied N times, each delay circuit outputs the inverted state of the initial state, and clock pulses are supplied N more times. Then, each delay circuit inverts the inverted state of the initial state and outputs the initial state.

That is, each delay circuit alternately outputs an initial state and its inverted state every time a clock pulse is supplied N times, thereby performing a (2×N) base counter operation.

The configuration of this counter is simple, but as mentioned above, the first problem is that the state of the counter, which is represented by the initial state and its inverted state, cannot be set to a certain predetermined state.
Even if the power is turned on again after the FF is turned off, the counter status before and after the power is turned off is different and undefined, making it impossible to detect.Secondly, during operation, clock pulses, electrodes, or each delay circuit Even if the state of the counter changes when a disturbance is applied to it, the change cannot be detected and the state of the counter cannot be returned to the state before the disturbance was applied. The shape (Fig. 1) made it unusable.

An example of an improved circuit to which a function of setting the initial state to a predetermined state was added is shown in FIG. 2.

Below, in order to simplify the explanation, the high potential power supply V of the operating amplitude
This is performed using positive logic in which DD is logic "1" (set state) and low potential power supply VSS is logic "0" (reset state).

In Fig. 2, a signal (S1) for setting the initial state is obtained from the output of an inverter I whose input terminal is the connection point of a capacitor C and a resistor H connected in series between VDD and VSS, and this signal and The NAND output of the final stage (Nth stage output) is given as the first stage input.

When the power switch is OFF, the connection point between C and R is at VSS, but as soon as the power switch is turned on, the connection point between C and R becomes VDD, and then decreases to VSS as time passes with the time constant being CR.

Therefore, the output state of the inverter I, that is, the signal S1 for setting the initial state, is VSS, that is, logic "0", from immediately after the power is turned on until the connection point potential becomes less than the inverting voltage of the inverter, and thereafter, it is VDD, that is, logic "1". be.

Since the signal (S1) for setting the initial state is always reset at first, the input state of the first stage is specified as set regardless of the original state.

If the clock pulse is supplied N times or more within this period, the output state of each delay circuit will be set.

When the signal (S1) for setting the initial state is set and the final stage output is negatively fed back to the first stage, it simultaneously operates as a normal (2×N) base counter.

FIG. 3 shows such operating waveforms.

In this case, the initial state of each delay circuit is a set state, and all other output states can be known from the output state of the final stage.

However, since the (2×N)-adic counter that has the function of setting such an initial state is exactly the same as the circuit shown in Figure 1 during operation, it does not have a self-recovery function in response to disturbances. Moreover, when this circuit is integrated into an integrated circuit, it is extremely difficult to form the capacitor C necessary for generating the signal for setting the initial state on the same integrated circuit chip. .

The present invention has been made in view of the above points. For example, a state setting signal for setting the state of each delay circuit is obtained from the output state of a (2×N) base counter as shown in FIG. 1, and the output of each delay circuit is obtained. It is possible to set the state to a certain specific state, and self-recovery is possible in response to disturbances using this state setting signal.Furthermore, this state setting signal can be used to change the input/output state of an arbitrary stage delay circuit as the Nth stage. (2×
N) This was done for the purpose of obtaining a base counter.

The details will be explained below using examples.

Generally, in a (2×N)-adic counter, which is constructed by negatively feeding back the output of the final stage of an N-stage cascade circuit consisting of N delay circuits to the input of the first stage, the delay circuit of a certain stage in a clock pulse If a set state is output at , a reset state is output after N clock pulse periods from that time, and a set state is output after another N clock pulse periods.

Therefore, within consecutive (2×N) clock pulse periods, a switch state in which the output goes from set to reset and a switch state in which the output goes from reset to set exist at least once with N clock pulse periods in between. become.

In other words, the set state after the switch is the set state of the input before the switch, and the reset state after the switch is the reset state of the input before the switch, so the input and output states are each logic "0".
A clock pulse period in which the input/output state is logic "1" and "1" and a clock pulse period in which the input/output state is logic "1" and "0", respectively, exist once separated by N consecutive pulse periods.

It goes without saying that each input state corresponds to the output state of the previous stage.

4 to 6 are state diagrams of a counter showing examples of state setting according to the present invention. FIG. 4 is a state diagram before state setting, and FIGS. 5 and 6 are diagrams showing the process of state setting.

At a timing ti of a certain clock pulse, for example, the output On of the final stage, that is, the Nth stage delay circuit is "1", and the output O of the (N-1)th stage delay circuit.

If -1 is "0", what is the normal situation? As shown in Figure 4, the output states U1~ from the first stage to the (N-2)th stage
U and 2 each become “0” due to the initial state or disturbance, etc.
, "1" indicates an uncertain state in which the state is unknown.

O as shown in FIG.

The state setting signal sD is set to “1” from “0” of - and “1” of On.
”, this “1” causes each output 01, 02 of at least the (N-2)th stage from the first stage at timing ti.
...If On-2 is reset, the states of U1 to Un-2, which were uncertain at ti, are all unified to "0" at ti +1.

Therefore, if this state setting is used, a counter that starts operating in an uncertain initial state will also become O when On-1 is "0".

is “1”, the output of all other delay circuits is “0”
The operating state is then specified.

Furthermore, even if this specified operating state changes due to a disturbance, the next time O becomes "0" and On becomes "1", 01
, o2...On-1 is "0" and On is "1"
Does it have a self-recovery function by being returned to a specific and normal operating state? It is.

In Fig. 6, when On-1 becomes "0" and On becomes "1", the state setting signal is set to "0", and the operating state is changed to 0, 02, etc. by "0" of this state setting signal.・On-
1 is a state diagram showing a setting example of a specific operating state in which 1 is "0" and On is "1"; FIG.

Another setting example is O when On-1 is "1" and Oo is "0", j O2,... On-1 is "1" and On
It is easy to understand from the above example that a specific state in which is "0" can be set.

Here, the output 0 of the first stage at timing ti 10, is "1" of the output ON of the final stage at timing ti.
Since it is uniquely determined as the inverted state "0" of "0", it is not necessarily necessary to reset the first stage output with the state setting signal, but in order to avoid complexity, the following description will be made assuming that the first stage is also reset with the state setting signal.

7 is a block diagram of the (2×N)-base counter having the state setting function shown in FIG. 5, and FIG. 8 is a block diagram of the (2×N)-base counter having the state setting function shown in FIG.

On-, is “1” and is 0. O1 r, 02 , . . . On-1
A block diagram of a (2×N)-adic counter with a state setting function that sets a specific operating state where On-1 is "1" and On is "0", respectively, and On-1 is "1" and On is "0" to "1". “I got the status setting signal 01,0,...On-
The block diagram of a (2×N)-adic counter that has a state setting function that sets a specific operating state where 1 is "1" and On is "0" is negative logic? The display is the same as in FIGS. 7 and 8 for positive logic, respectively.

The (N-1)th delay circuit from the first stage in FIG. 7 uses clock pulses such as read pulse φ1 and read pulse φ
2 as the same source and has a first input terminal (1) which receives the output of the previous stage as an input, and a second input terminal (2) to which a state setting signal sD is applied.

Both input states and state setting signals at timings ti and ti1 of a certain clock pulse of this delay circuit are respectively (1-1), (2) and SD (iL output state is 0 (i)). Then, this delay circuit becomes 0 (i) = II Ci -1) as is clear from the process of setting the state above.
'I2 (i) or 0(i)-L(iyo)-] It has the function of being a buyer's shoulder.

Hereinafter, such a delay circuit will be abbreviated as a first delay circuit (D).

The Nth stage delay circuit has only a first input terminal ■1 to which the clock pulse is commonly applied and inputs the output of the (N-1)th stage.
) and will be referred to as the second delay circuit (D2).
It is abbreviated as.

In Figure 7, the (N-1)th stage (Xn-1) is the first
However, the supply of the state setting signal (SDX) may be stopped as a second delay circuit (D2).

In FIG. 8, at least the final stage (Yn) is
A delay circuit (D2) is used.

And at least the first stage (Y1) to (N-2) stage (Y
In this case, the delay circuit used for (n-2) is O(i)=
■l(1-1)・■2(i) or 0(i)=I1・(i
-1)'・SD (i) The function is required,
A circuit having this function is abbreviated as a third delay circuit (D3).

The (N-1)th stage (Yn,) may use either the second or third delay circuit (D2 or D3) as in FIG.

The state setting signal (SDX) used in FIG. 7 has two inputs: the input state of the final stage and the inverted state of the output state.
It is easiest to obtain it as an output signal of an OR gate or an AND signal of the inverted state of the input of the final stage and the output state.

The state setting signal (SDY) used in FIG. 8 is the output signal of a NAND gate whose two inputs are the inverted state of the input state and the output state of the final stage, or the OR of the input state of the final stage and the inverted state of the output. The easiest way to obtain it is as a signal.

FIG. 9 is an operation waveform diagram of the circuit of FIGS. 7 and 8.

Is it the same figure as a clock pulse? In addition to using φ1 and φ2 with different phases as shown as the reading pulse and readout pulse of the delay circuit, respectively, it is also possible to use a number of clock pulses with different phases or to read this CP using one clock pulse CP. Pulse (φ1)
It is also possible to use a one-phase system in which the inverted pulse CP is used as the readout pulse (φ2), or to use the pulses having different frequencies as φ and φ2.

These operations can be considered that the previous φ1 closest to φ2 acts as a read pulse for that φ2, and the subsequent φ2 closest to φ1 reads the input state read by that φ1.

In the above, as shown in FIGS. 7 and 8, the state setting signal (SDX or SDY) is applied to at least the (N-2)th stage (Xn-2 or Y) from the first stage (X, or Y1).

The explanation will be simplified by assuming that it supplies up to -2), but the functional conditions will be described in more detail as follows.

That is, if N is an even number, the state setting signal is supplied from the first stage at least? N-2)/2nd stage, or if N is an odd number, from the first stage to at least (N-1)/2nd stage is sufficient, and the second delay circuit is sufficient for the other stage delay circuits. It is.

FIG. 10 is a (2×N)-adic state diagram explaining this sufficient condition.

The stages up to the jth stage in the figure are first delay circuits that receive the state setting signal as input, and the stages from the (j+1)th stage to the final stage are second delay circuits.

Now, when On-1 becomes "0" and on becomes "1" at timing ti of a certain clock pulse, the state setting signal sD becomes "1" as described above, and the outputs 01, 0 of the Jth stage from the first stage.
, . . . 0. are each “0”.

At this time, the outputs from the (J+1)th stage to the (N-2)th stage remain uncertain.

These are respectively U1...Ul...
・・・・・・Denoted by Uk (k = n-2-j), U
1...Ul...Uk is "0" or "
It has one of the logical values of 1''.

However, in general, there is at least one logic "1" in these uncertain states (if all are "0", the state is fixed), so U1...Ul is "0"
”, it is possible to consider that Ul is “1” (l=1 to k) without loss of generality.

Next, at timing t, the output O of the first stage becomes "0", which is the inverted state of "1" of the output On of the final stage, and from the first stage (
The outputs of the j+1)th stage all become “0”, and Oj+2 to O
U1 to Uk are sequentially shifted to n, and "0" is sequentially shifted to Oo.

Therefore, the clock pulse time ti-1-(k-1+2) when the clock pulse is applied (k-d+2) times from t1
), the states where Ul-, is "0" and Ul is "1" appear as On-1 and On, respectively, so that the outputs from the first stage to the Jth stage are 0, ,02,...・
0. becomes all "0" again.

Therefore, the uncertain state Ul+1 that has been shifted to each stage
, U l +2...,■T and the state that follows it"
1" are all reset by "0" of Ol-1 and "1" of Ul, that is, if the relationship J)k-l+1 is established, then only the output state of the final stage is " 1”
The output state of all other stages can be set to "0".

Therefore, when l is the minimum in jh(N-1-l)/2 found from N=j+2+k and k≦j+1-1, when the minimum value that j can take is maximum, that is, l-1, J>(N-2 )
/2.

J must be an integer, so the minimum j is j = (N-2)/2 if N is even, and j = (N-2) if N is odd.
1)/2.

FIGS. 11 and 12 are block diagrams of a general counter incorporating the above idea, and correspond to FIGS. 7 and 8, respectively.

j in the figure is an integer that satisfies the above conditions, and the delay circuits from the (j+1)th stage to the (N-1)th stage may be either the first or second delay circuit.

13 to 20 show an example of the second delay circuit, which is particularly suitable for large-scale integration (LSI) and is constructed using a G-FET.

Figures 13 and 14 show cases in which the load is an enhancement type, with a single channel such as a P-channel type G-FET, and Figures 15 and 16 show cases where the load is a depletion type and consists of a single channel, such as a P-channel IG-FET. Figures 17 and 18 show both P and N channel type IG-FE.
Complementary one using T, Figures 19-20 are other complementary IG
-It uses FET.

Each of these examples of delay circuits is constructed using the characteristics that the gate input of the IG-FET has a high input impedance (1000 MΩ or more) and is capacitive, and is generally referred to as a dynamic type.

These circuits have a lower limit of the clock pulse frequency for normal operation, so stabilizing circuits are added based on Figures 13 to 20, but even those with these stabilizing circuits cannot be used as a second delay circuit. Needless to say, it can be used.

Further, the first or third delay circuit can be easily constructed from the second delay circuit by a person who knows IG-FET circuits.

Furthermore, in the above explanation, when feeding back the output of the final stage, an inverter is placed at the input of the first stage, but if the inverter is placed at the input of the first stage as shown in Figs. It can be placed at any stage between the first stage and the last stage.

21 has the same function as FIG. 11, and FIG. 22 has the same function as FIG. 12.

These operations correspond to the operation waveforms 01 to 0 shown in FIG.
Only the j-1 waveform is inverted and replaced.

FIGS. 23 and 24 are obtained as modifications of FIGS. 21 and 22, respectively.

In this case, the fourth delay circuit (D4) shown in FIG.
The function of is 0 (i) -L (i −t )+
I2(i) or 0(i)-It(i-1)
+SD(i), and the function of the fifth delay circuit (D5) shown in FIG. 24 is 0(i)=I1(i −
t) +Tπ stone or 0(i) -It(i-l)
This is Tadashi Toda.

The operating waveforms in FIGS. 23 and 24 are the same as those in FIGS. 21 and 22, respectively.

Also, in the above explanation, the delay circuits were given names such as the first stage to the final stage, but since the final stage is connected to the first stage and is connected in a ring, any stage can be considered the final stage in terms of circuit layout. The above explanation can be applied to the stage following this as the first stage.

That is, the final stage in the present invention can be defined as a delay circuit to which a state setting signal is set based on the input/output state of that stage.

In addition, the state setting signal of the (2×N) base counter of the present invention is the pulse width of the basic cycle of the clock pulse (pulse width for one base).
Since a setting signal is generated in
It is extremely effective for logic design if used as a pulse indicating the final state of the xN)-adic counter.

Further, in each of the above embodiments, the state setting signal is set as the final (2×N) clock pulse period, but it can also be set as the first clock pulse period.

Although the above description has been made for a (2×N)-base counter, the present invention can also be applied to a (2N-P)-base counter obtained by increasing the feedback loop of the final stage output from the first stage to the P stage. Various modifications within the scope of the invention are also possible.

The present invention is as described above, and in addition to providing the basic requirements of this type of counter, such as identifying the initial state, detecting the operating state, and self-restoring against disturbances, it is also easy to integrate into an integrated circuit. It has the following effects.

[Brief explanation of the drawing]

Figure 1 is a principle diagram of a general (2xN)-base counter, Figure 2 is a block diagram of a conventional (2xN)-base counter, Figure 3 is its operating waveform diagram, and Figures 4-6 are from this book. A state diagram of a counter showing an example of the state setting of the invention, FIGS. 7 and 8 are block diagrams of an embodiment of the invention, FIG. 9 is an operation waveform diagram thereof, and FIG. 10 is a counter state setting example of another state setting example of the invention. State diagram, 11th-12th
The figure is a block diagram of an embodiment that performs the operation shown in Figure 10, and Figure 13.
20 are circuit diagrams showing examples of delay circuits used in the circuit of the present invention, and FIGS. 21 to 24 are block diagrams showing modified examples of the present invention. X, ~X n 5 y, ~Yn...delay circuit,
■1...First input, ■2...Second input.

Claims (1)

[Claims] 1. A plurality of delay circuits that are sequentially connected in cascade and are controlled by clock pulses, an inverting circuit that inverts the output of the final stage delay circuit and supplies it to the input of the first stage delay circuit, and an input signal to the final stage delay circuit. and a generation circuit that receives the output signal and generates a state setting signal, and supplies this state setting signal to other delay circuits other than the final stage delay circuit to reset the other delay circuits, and 1. A counter comprising means for resetting the outputs of all delay circuits at clock pulse timing.