JPS5895809A - Volume variable type laminated chip condenser - Google Patents

Volume variable type laminated chip condenser

Info

Publication number
JPS5895809A
JPS5895809A JP19392281A JP19392281A JPS5895809A JP S5895809 A JPS5895809 A JP S5895809A JP 19392281 A JP19392281 A JP 19392281A JP 19392281 A JP19392281 A JP 19392281A JP S5895809 A JPS5895809 A JP S5895809A
Authority
JP
Japan
Prior art keywords
electrode
variable type
laminated chip
volume variable
type laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19392281A
Other languages
Japanese (ja)
Inventor
涼 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19392281A priority Critical patent/JPS5895809A/en
Publication of JPS5895809A publication Critical patent/JPS5895809A/en
Pending legal-status Critical Current

Links

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は容j1crr変型&層チップコンデンサに関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a j1 crr modified & layered chip capacitor.

高伽幀性機能部品として混成集積回路のW@要が多くな
り、今後も烏性能・^品質の特徴を生かしてますます広
がっていくことが弯えられる。
Hybrid integrated circuits are becoming increasingly popular as highly functional functional components, and it is expected that they will continue to spread further in the future by taking advantage of their characteristics of performance and quality.

この混成iJA積回路には、小型化・烏性能化からチッ
プ抵抗、チップコンデンサを用いることが重装となって
きた。このなかで抵抗のトリミングはレーザあるいはサ
ンドブラストなどを用いて端止ルテニウムを主成分とす
る抵抗体を切〜1・除去することによって簡単に行なう
ことかできるが、チップコンデンサではこのような方法
を用いることかできなかった。
This hybrid iJA product circuit has become heavily equipped with chip resistors and chip capacitors for miniaturization and improved performance. Trimming of the resistor can be easily done by cutting or removing the end-stopping ruthenium-based resistor using a laser or sandblasting, but this method is not used for chip capacitors. I couldn't do anything.

そこで従来、第1図に示すように、上部からレーザ光あ
るいはサンドブラスト法(イ)を用いて誘電体fg4 
(13と内部を極(2)とを共に溶融飛散あるいは研削
除去することによってコンデンサIIjI成都の一部を
除去する方法が提案されている。なお(8aXlb)は
端子電極である。ところがこのような方法では、容鳳値
の調節は可能であるも雫の、内部電極(2)と誘電体層
(1)とを−緒に加工するため、対向する内部電極(2
1(21を短絡させたり、あるいは破壊された内部電極
(2)の一部が電極粉として残り、絶縁耐圧が低下した
りする問題があった。特に、積層構造をとるチップコン
デンサではグリーンシート法あるいは印刷法によって数
10μmの誘電体層+11を有するチップコンデンサが
一般化してき°Cいるが、このようなものでは上記問題
点が顕著に発生し、上記従来方法を用いることは困難で
あった。
Therefore, conventionally, as shown in Fig. 1, dielectric material fg4 is
A method has been proposed in which a part of the capacitor IIjI Chengdu is removed by melting and scattering or polishing off both the electrode (13 and the inside of the electrode (2). Note that (8aXlb) is the terminal electrode. In this method, the capacitance value can be adjusted, but since the internal electrode (2) and the dielectric layer (1) are processed together, the opposing internal electrode (2)
1 (21), or a part of the broken internal electrode (2) remains as electrode powder, reducing the dielectric strength. In particular, the green sheet method is used for chip capacitors with a laminated structure. Alternatively, chip capacitors having a dielectric layer of several tens of micrometers have become commonplace by printing methods, but such capacitors suffer from the above-mentioned problems, making it difficult to use the conventional methods described above.

本発明は上記の点に鑑み、対向する内部電極のショート
や絶縁耐圧の低下を発生することなく容゛赫に容重の調
節を行なうことのできる容量可変型積層チップコンデン
サを提供することを目的とする。
In view of the above points, an object of the present invention is to provide a variable capacitance multilayer chip capacitor that can greatly adjust the capacitance without causing a short circuit between opposing internal electrodes or a decrease in dielectric strength. do.

すなわち本発明は、両端に端子電極を有する積層型コン
デンサの積層方向両面のうち少なくとも一方の向に、罰
記端子電極のうち一方の端子電極に接続された膜状の表
向電極を設け、この表面電極を被覆する透明な保i!1
膜を設けたものであり、表向電極をレーザあるいはサン
ドブラストで切断することにより容量調節できるので、
対向する内部電動のショートや絶縁耐圧の低下を生じる
ことがなく、高い信頼性を得ることができる。
That is, the present invention provides a film-like surface electrode connected to one of the penal terminal electrodes on at least one of both surfaces in the stacking direction of a multilayer capacitor having terminal electrodes at both ends. A transparent coating covering the surface electrode! 1
It is equipped with a membrane, and the capacity can be adjusted by cutting the surface electrode with a laser or sandblasting.
High reliability can be achieved without causing a short circuit or a drop in dielectric strength voltage between opposing internal electric currents.

以下本発明の一実施例を図面に基づいて説明す6 @ 
h 2 E ニおいて、(4)は両端・′こ端面電極(
5a)(5b)を1する&鵬型コンデンサであり、この
積層型コンデンサ(4)は、誘電体3m(6)と内部電
極(7)とが交互に数層〜数十層積層されたものである
。前記複数の内部電111(7)は、一方のjIIIi
IDwt極(5a)に接続されkものと他方の端面W極
(5b)に接続されたものとが交互に配電されており、
複数組の対向vIL極を構成している。創記禎層型コン
デンサ(4)の伽膚方同1111面のうち一方の間には
、一方の端面wL檎(5a)に接続された膜状5の表面
電極(6)が形成されており、この表向1i極(81は
耐環境特性を向上させるために透明な保護膜(9)によ
り被覆されている。この保護膜(9)としでは、ガラス
あるいは′44機材料であるアクリル、エポキシ、フェ
ノール、ポリイミドなどが逸しており、このうちガラス
コーティングが信頼性の面から最も好ましい。
An embodiment of the present invention will be described below based on the drawings6 @
h 2 E d, (4) is the end face electrode (
5a) (5b) is a 1&Peng type capacitor, and this multilayer capacitor (4) has several to tens of layers of dielectric material (6) and internal electrodes (7) alternately laminated. It is. The plurality of internal voltages 111(7) are connected to one jIIIi
Power is alternately distributed between the k connected to the ID wt pole (5a) and the k connected to the other end W pole (5b),
A plurality of pairs of opposing vIL poles are configured. A membrane-shaped surface electrode (6) connected to one end surface (5a) is formed between one of the 1111 surfaces of the layered capacitor (4). , this surface 1i electrode (81) is covered with a transparent protective film (9) to improve its environmental resistance.This protective film (9) may be made of glass, acrylic or epoxy material. , phenol, polyimide, etc. are lacking, and among these, glass coating is the most preferred from the standpoint of reliability.

上記構成において、容嵐値を調節する身こ際しては、表
面電極(8)を例えば矢印(ロ)方向に破MA&*部分
で切断する。かくし”C表面電極(8)の有効面積をに
更することにより、所望の容Jlt値か得られる。この
斗リミング方法としては、鉤えばNd;YAGレーザや
CO,レーザ卿のレーザを用いる方法、あるいはS i
C* A1103粉末を用いたサンドブラスト法が好ま
しい。
In the above configuration, in order to adjust the storm value, the surface electrode (8) is cut, for example, in the direction of the arrow (b) at the broken MA&* portion. By increasing the effective area of the hidden "C" surface electrode (8), the desired volume Jlt value can be obtained.This rimming method uses a Nd;YAG laser, a CO, or a laser. , or S i
Sandblasting using C* A1103 powder is preferred.

以下に具体的実九例を説明する。Nine specific examples will be explained below.

下記fIs1表に示すように、誘電体層としてBaTi
01を用い、表向電極としてAg/pd系ペーストを用
いた、チップサイズ8.2X1.6X1.2mlの、互
L’l(槙膳数の異なる8種類の容量可変型積層チップ
コンデンサを製作した。なお表向電極は一方の自のみに
設けた。また保amはガラスコート及びエポキシ−脂を
用い、ガラスコートは500”C−10分焼成、iだエ
ポキシ樹脂は150”C−1時間の硬化条件とした。
As shown in the fIs1 table below, BaTi is used as the dielectric layer.
Eight types of variable capacitance multilayer chip capacitors with different chip sizes of 8.2 x 1.6 x 1.2 ml and different numbers of chips were fabricated using Ag/PD paste as the surface electrode. The surface electrode was provided only on one side. Glass coat and epoxy resin were used for the insulation. The glass coat was baked at 500"C for 10 minutes, and the epoxy resin was baked at 150"C for 1 hour. curing conditions.

爲1表 上記81IiA類の春型可変型ll1l1層チップコン
デンサの表向電極を、Nd;YAGレーザを用いて、端
からgmm比で174づつ順次切断していくことにより
、−8図をζ示す如く階段状の@臘41L変化を得た。
1. By sequentially cutting the surface electrodes of the above-mentioned 81IiA class variable spring-type ll1l single-layer chip capacitors using a Nd; A step-like @臘41L change was obtained.

゛またこのトリミング方法により表向it―の切断を行
なった容量可変形積層チップコンデンサに対し’(,6
0℃−95%(7)高温^湿中にてocsov;に連続
通電する寿命試験を行なったが、切断された表向電極が
互いに短絡する現象はみられなかった。
``Also, for variable capacitance multilayer chip capacitors whose ostensible IT- has been cut by this trimming method'' (,6
A life test was conducted in which the electrodes were continuously energized at 0° C.-95% (7) at high temperature and humidity, but no phenomenon was observed in which the cut surface electrodes were short-circuited to each other.

以上説明したように、本発明にかかる容量司良型積層チ
ップコンデシサによれば、対向する内部電極の短絡や絶
縁耐圧の低下を発生させることなく容易に@aを調節で
き、高い信頼性を得ることができる。
As explained above, according to the capacitive type multilayer chip capacitor according to the present invention, @a can be easily adjusted without shorting the opposing internal electrodes or reducing the withstand voltage, and high reliability can be achieved. Obtainable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の積層チップコンデンサのIjT曲図、第
2図囚は本発明の一実施例における容量可変型積層チッ
プコンデンサの断面図、同図Φ)は向平向図、第8図は
本発明の具体゛実施例における容量可変型積層チップコ
ンデンサの表向電極の切断朧と容量及びtan aとの
関係の説明図である。 (4)・・・積層型コンデンサ、(5m)(5b)・・
・端面電極、(8)・・・表向電橋、(9)・・・保護
膜。 代理人   森 本 義 弘 第1図 イ 第2図 6  ”  4   、、。 第3図 切断量
Fig. 1 is an IjT diagram of a conventional multilayer chip capacitor, Fig. 2 is a cross-sectional view of a variable capacity multilayer chip capacitor according to an embodiment of the present invention, Φ) is a horizontal view, and Fig. 8 is a cross-sectional view of a variable capacitance multilayer chip capacitor according to an embodiment of the present invention. FIG. 4 is an explanatory diagram of the relationship between the cutting blur of the surface electrode of the variable capacitance type multilayer chip capacitor, the capacitance, and tana in a specific embodiment of the invention. (4)...Multilayer capacitor, (5m) (5b)...
・End face electrode, (8)... Surface electric bridge, (9)... Protective film. Agent Yoshihiro Morimoto Figure 1 A Figure 2 6 ” 4,... Figure 3 Cutting amount

Claims (1)

【特許請求の範囲】[Claims] 1、  jIAl端に端子*mを1する積層型コンデン
サの積層方向両面のうち少なくとも一方の面に、8iI
記端子電画のうち一方の端子電極に接続された膜状の表
面電極を設け、この表面11IL極を被覆する透明な保
護膜を設けた@嵩司変型槓層チップコンデンサ。
1. 8iI on at least one of both sides in the stacking direction of the multilayer capacitor with terminal *m1 at the jIAl end.
@Takashi modified layered layer chip capacitor provided with a film-like surface electrode connected to one terminal electrode of the terminal electrode, and provided with a transparent protective film covering the surface 11IL electrode.
JP19392281A 1981-12-01 1981-12-01 Volume variable type laminated chip condenser Pending JPS5895809A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19392281A JPS5895809A (en) 1981-12-01 1981-12-01 Volume variable type laminated chip condenser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19392281A JPS5895809A (en) 1981-12-01 1981-12-01 Volume variable type laminated chip condenser

Publications (1)

Publication Number Publication Date
JPS5895809A true JPS5895809A (en) 1983-06-07

Family

ID=16315966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19392281A Pending JPS5895809A (en) 1981-12-01 1981-12-01 Volume variable type laminated chip condenser

Country Status (1)

Country Link
JP (1) JPS5895809A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0422116A (en) * 1990-05-17 1992-01-27 Murata Mfg Co Ltd Frequency adjusting method of electronic parts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0422116A (en) * 1990-05-17 1992-01-27 Murata Mfg Co Ltd Frequency adjusting method of electronic parts

Similar Documents

Publication Publication Date Title
US7605683B2 (en) Monolithic electronic component
JP6923118B2 (en) Multilayer ceramic electronic components and their manufacturing methods
JP3527531B2 (en) Package type solid electrolytic capacitor
JP2006269876A (en) Anti-electrrostatic component
JPS5923458B2 (en) composite parts
JPH11273950A (en) Laminated chip coil part
JPS5895809A (en) Volume variable type laminated chip condenser
JPH1140459A (en) Composite electronic parts
JPS6120739Y2 (en)
JP2002043166A (en) Electronic component
JPS6243523B2 (en)
JPS5969902A (en) 3-terminal laminated varistor
JPS6210981Y2 (en)
JP2001167968A (en) Laminated ceramic capacitor
JPH11260653A (en) Laminated electronic component and manufacturing method therefor
JPH0831393B2 (en) Multilayer ceramic capacitor with fuse
JPH0917689A (en) Printing capacitor and its manufacture
JPS6015277Y2 (en) thick film varistor
JPS6225873Y2 (en)
JP2961925B2 (en) Circuit board
JPH0134336Y2 (en)
JPH05226721A (en) Electrostrictive effect device
JPS63102218A (en) Laminated multiterminal electronic component
JPS6050046B2 (en) How to trim composite parts
JPH0195591A (en) Multylayered ceramic substrate and manufacture thereof