JPS5894242A - Suppressing device of impulsive noise - Google Patents

Suppressing device of impulsive noise

Info

Publication number
JPS5894242A
JPS5894242A JP19171581A JP19171581A JPS5894242A JP S5894242 A JPS5894242 A JP S5894242A JP 19171581 A JP19171581 A JP 19171581A JP 19171581 A JP19171581 A JP 19171581A JP S5894242 A JPS5894242 A JP S5894242A
Authority
JP
Japan
Prior art keywords
signal
circuit
point
input terminal
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19171581A
Other languages
Japanese (ja)
Other versions
JPS6312409B2 (en
Inventor
Yoshiro Sugai
菅井 義郎
Eiji Ueno
上野 栄治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP19171581A priority Critical patent/JPS5894242A/en
Publication of JPS5894242A publication Critical patent/JPS5894242A/en
Publication of JPS6312409B2 publication Critical patent/JPS6312409B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H40/00Arrangements specially adapted for receiving broadcast information
    • H04H40/18Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/72Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/34Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
    • H03G3/345Muting during a short period of time when noise pulses are detected, i.e. blanking

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

PURPOSE:To eliminate the impulsive noise out of the audible signal without producing noises, by eliminating also the pilot signal when the impulsive noise is eliminated through an arithmetic circuit. CONSTITUTION:The signal having a delayed FM wave detection output which is applied to the input emerges at an output point A of an LPF1. The output of the LPF1 is applied to the minus input terminal of one side of a subtractor circuit 7. The pilot cancel signal is applied to the other minus input terminal of the circuit 7. The pilot signal in the composite signal is cancelled at the circuit 7. In such a constitution, a mono-multi 6 turns off a switch circuit 10 when the impulsive noise occurs in the composite signal. When the circuit 10 is turned off, the waveforms at points A and B are transmitted to a point C via the level holding circuits 8 and 9. Therefore the impulsive noise emerges at the point C, and a waveform obtained by eliminating the pilot signal and the impulsive noise from the waveform emerging at the point A emerges at the output point D of the circuit 7.

Description

【発明の詳細な説明】 本発明は、車載用FM受信機においてパルス性ノイズを
有効に除去するためのパルス性ノイズ抑圧装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse noise suppression device for effectively removing pulse noise in a vehicle-mounted FM receiver.

従来の斯かる装置は第1図に示すように構成されている
。図において、lは信号遅延手段として働くローパスフ
ィルタ(以下り、P、FトII)記する)で、ノイズ処
理を行うのに必要な時間だけ信号を遅延する。ゲート2
はパルス性ノイズが入力されたときのみ信号を一瞬遮断
するように働き、レベルホールド回路3は信号がゲート
2によって遮断されている間その出力レベルを遮断直前
の信号レベルに保持するように働く。
Such a conventional device is constructed as shown in FIG. In the figure, l is a low-pass filter (hereinafter referred to as P, F, and II) that functions as a signal delaying means, and delays the signal by the time necessary to perform noise processing. gate 2
works to momentarily cut off the signal only when pulse noise is input, and the level hold circuit 3 works to hold its output level at the signal level immediately before the cutoff while the signal is cut off by the gate 2.

4は100KHz位の遮断周波数を有するバイパスフィ
ルタ(以下H,P、Fと略記する)で、FM検波器(図
示せず)からの検波出力からノイズ成分のみを取り出す
ように働く。AGC付ノイズアンプ5はH,P、F4の
出力を増幅し、ノイズエネルギーが成る一定レベルを越
えるとAGCが働き、ゲインを下げるようになっている
。これは弱電界などでホワイトノイズ成分が増加したと
き、これによってゲート2が頻繁に動作されて信号が途
切れるのを防ぐためのものである。単安定マルチバイブ
レータ(以下単安定マルチと略記する)6は、ノイズア
ンプ5の出力が成る一定値より大きくなるとゲート2を
駆動するための一定幅のパルス信号を発生する。
Reference numeral 4 denotes a bypass filter (hereinafter abbreviated as H, P, and F) having a cutoff frequency of about 100 KHz, which functions to extract only noise components from the detection output from the FM detector (not shown). The noise amplifier 5 with AGC amplifies the outputs of H, P, and F4, and when the noise energy exceeds a certain level, the AGC operates to lower the gain. This is to prevent the gate 2 from being operated frequently and the signal being interrupted when the white noise component increases due to a weak electric field or the like. A monostable multivibrator (hereinafter abbreviated as monostable multi) 6 generates a pulse signal of a constant width for driving the gate 2 when the output of the noise amplifier 5 exceeds a constant value.

上述のノイズ抑圧装置において、FM検波器からの信号
が第2図(alに示すような比較的低い周波数のもので
ある場合、破線で示す期間ゲート2が一瞬閉じられると
、レベルホールド回路3の出力には、第2開山)に示す
ようにゲート2が閉じられたときのレベルが保持された
信号が発生される。
In the above-mentioned noise suppression device, when the signal from the FM detector is of a relatively low frequency as shown in FIG. At the output, a signal is generated that maintains the level when the gate 2 is closed, as shown in the second opening.

こ、の場合、レベルホールド回路3は何ら不都合なく働
き、ノイズが発生することもない。
In this case, the level hold circuit 3 functions without any problem and no noise is generated.

ところが、第3図1a)に示すようなステレオパイロッ
ト信号が破線で示す期間−瞬ゲート2で遮断されると、
第3図(b)に示すようにゲート2が遮断されている期
間DCレベルで保持された信号がレベルホールド回路3
の出力に得られ、波形が不連続となるため、ノイズが発
生するようになる。これは、パイロット信号の周波数が
高いため、ゲート2が遮断している時間が半波長や1波
長に及んでしまい、単純にDC電位で補正を行うレベル
ホールド回路3ではうまく補正で−きないためである。
However, when the stereo pilot signal as shown in FIG. 3 1a) is interrupted during the period indicated by the broken line - instantaneous gate 2,
As shown in FIG. 3(b), the signal held at the DC level during the period when the gate 2 is cut off is transferred to the level hold circuit 3.
Since the waveform is discontinuous, noise is generated. This is because the frequency of the pilot signal is high, so the time the gate 2 is cut off extends to half a wavelength or one wavelength, and the level hold circuit 3, which simply corrects with DC potential, cannot correct it well. It is.

本発明は上述した点に鑑みてなされたもので、その目的
とするところは、ステレオパイロット信号を含む可聴信
号中より、ノイズを発生することなくパルス性ノイズを
除去することのできるパルス性ノイズ抑圧装置を提供す
ることにある。
The present invention has been made in view of the above-mentioned points, and an object of the present invention is to suppress pulse noise by removing pulse noise from an audible signal including a stereo pilot signal without generating noise. The goal is to provide equipment.

以下本発明を第4図以降を参照して説明する。The present invention will be explained below with reference to FIG. 4 and subsequent figures.

第4図は本発明によるパルス性ノイズ抑圧装置の実施例
を示すブロック図で、図中り、P、Fl。
FIG. 4 is a block diagram showing an embodiment of the pulse noise suppressing device according to the present invention.

H,P、F4 、AGC付ノイズアンプ5及び単安定マ
ルチ6は第1図に示した従来の装置のものと同じもので
よい。
H, P, F4, noise amplifier with AGC 5, and monostable multi-function device 6 may be the same as those in the conventional device shown in FIG.

L、P、  Ftの出力点Aには、その入力に加えられ
るFM検波出力を遅延した第5図(alに示すような信
号が現われる。この信号はパイロット信号と可聴信号と
からなるコンポジット信号にパルス性ノイズが重畳した
ものである。L、P、Flの出力は、その中のパイロ7
)信号がバイパスされ、パイロット信号を必要とする回
路に供給されると共に、引算回路7の一方の一入力端子
に印加されている。引算回路7の他方の一入力端子(こ
れを点Bとする)には、第5図(b)に示すようなパイ
ロットキャンセル用信号(以下パイキャン信号という)
が加えられている。このパイキャン信号は上記コンポジ
ット信号中のパイロット信号と逆相になっているため、
引算回路7においてコンポジット信号中のパイロ7)信
号のキャンセルが行われる。
At the output point A of L, P, and Ft, a signal as shown in Figure 5 (al) appears, which is the delayed FM detection output applied to the input. This signal is a composite signal consisting of a pilot signal and an audible signal. The outputs of L, P, and Fl are the result of superimposed pulse noise.
) signal is bypassed and supplied to the circuit requiring the pilot signal, and is applied to one input terminal of the subtraction circuit 7. The other input terminal of the subtraction circuit 7 (this is referred to as point B) receives a pilot cancellation signal (hereinafter referred to as a pie-can signal) as shown in FIG. 5(b).
has been added. This pie-can signal is in opposite phase to the pilot signal in the composite signal, so
In the subtraction circuit 7, the pyro 7) signal in the composite signal is canceled.

上記引算回路7の両−入力端子と十入力端子(これを点
Cとする)間にはレベルホールド回路8及び9がそれぞ
れ接続され、かつ十入力端子とアース間には通常オンし
ているスイッチ回路lOが接続されている。従って、上
記点Cは通常交流的にアースに落ちている。なお、スイ
ッチ回路10は単安定マルチ6が発生するパルス信号に
よってオフ制御されるようになっていて、スイッチ回路
10がオフすると、点Cのインピーダンスが上がるよう
になる。
Level hold circuits 8 and 9 are connected between both input terminals and the ten input terminal (point C) of the subtraction circuit 7, and are normally turned on between the ten input terminal and the ground. A switch circuit IO is connected. Therefore, the point C is normally grounded in an alternating current manner. Note that the switch circuit 10 is turned off by a pulse signal generated by the monostable multi 6, and when the switch circuit 10 is turned off, the impedance at point C increases.

上述のような構成により、コンポジット信号中に第5図
(alに示すようなパルス性ノイズが現われると、単安
定マルチ6が一定幅のパルス信号を発生してスイッチ回
路10をオフさせる。このスイッチ回路lOのオフ動作
は、L、P、Flを通過されて遅延された点Aのコンポ
ジット信号に対しては、パルス性ノイズが立上がる前の
破線で示す時点t1で行われる。そして、このスイッチ
回路10のオフにより、上述したように点Cのインピー
ダンスが上がるため、点Aの波形はレベルホールド回路
8を介し、点Bの波形はレベルホールド回路9を介して
それぞれ点Cに伝達される。
With the above-described configuration, when pulse noise as shown in FIG. The OFF operation of the circuit 1O is performed at the time t1 shown by the broken line, before the pulse noise rises, for the composite signal at point A that has been passed through L, P, and Fl and delayed. When the circuit 10 is turned off, the impedance at the point C increases as described above, so the waveform at the point A is transmitted to the point C via the level hold circuit 8, and the waveform at the point B is transmitted to the point C via the level hold circuit 9.

上記点Cの波形はスイ・ノチ回路10がオフする直前の
点CのDC電位から始まり、しかもレベルホールド回路
8を介して伝達される信号中のパイロット信号はレベル
ホールド回路9を介して伝達されるパイキャン信号によ
ってキャンセルされるため、点Cには第5図(C1に示
すようなパルス性〕ィズに相当する波形が現われる。そ
してこの波形が引算回路7の逆相入力端子に加えられて
いるため、引算回路7の出力点りには、点Aに現われる
波形からパイロット信号とパルス性ノイズとを除去した
第5図(diに示すような波形が現われる。なお、点り
の波形はスイッチ回路10がオフする直前のレベルをス
イッチ回路IOがオンする時点t2まで保持している。
The waveform at point C starts from the DC potential at point C just before the switch circuit 10 turns off, and the pilot signal in the signal transmitted through the level hold circuit 8 is transmitted through the level hold circuit 9. 5 (pulse nature as shown in C1) appears at point C. This waveform is then applied to the negative phase input terminal of the subtraction circuit 7. Therefore, at the output point of the subtraction circuit 7, a waveform as shown in FIG. holds the level immediately before the switch circuit 10 turns off until time t2 when the switch circuit IO turns on.

上述のように本発明によるパルス性ノイズ抑圧装値では
、パルス性ノイズを除去する際パイロット信号も同時に
除去しているため、出力にはパイロット信号が途中で切
られた形の信号が現われることがない。従って、パイロ
ット信号が途中で切られることによる波形歪とそれに伴
うノイズの発生がなくなる。
As mentioned above, in the pulse noise suppression system according to the present invention, when removing pulse noise, the pilot signal is also removed at the same time, so a signal in which the pilot signal is cut off may appear in the output. do not have. Therefore, waveform distortion caused by the pilot signal being cut off midway and generation of noise associated with it are eliminated.

また、本発明による装置では、引算回路又は加算回路で
よい一般的な演算回路の使用によりパイロット信号とノ
イズの両方のキャンセルを行っていて、しかもこれをゲ
ート回路を使わずただ1個のスイッチ手段の使用により
行っているため、回路構成が簡単になるという実用上有
効な効果も得られる。
Furthermore, the device according to the present invention cancels both the pilot signal and the noise by using a general arithmetic circuit, which may be a subtraction circuit or an addition circuit. Since this is done by using means, a practically effective effect of simplifying the circuit configuration can also be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の装置の一例を示すブロック図、第2図(
al及び(b)並びに第3図(a)及び山)は第1図の
装置の動作を説明するための波形図、第4図は本発明に
よる装置の一実施例を示すブロック図、第5図(al乃
至(diは第4図の装置の各点の波形を示す波形図であ
る。 ■・・・ローパスフィルタ(遅延手段)、4・・・バイ
パスフィルタ、5・・・AGC付ノイズアンプ、6・・
・単安定マルチバイブレータ、7・・・引算回路(演算
回路)、8.9・・・レベルホールド回路、10・・・
スイッチ回路(スイッチ手段) 特許出願人      パイオニア株式会社(a) (C) ハ1ルズー11ノイズ (b) ↑+     t2 トヒ 1 ハ゛イAイン阿イ志号 (d)
Figure 1 is a block diagram showing an example of a conventional device, and Figure 2 (
al and (b) and FIG. 3(a) and crest) are waveform diagrams for explaining the operation of the device in FIG. 1, FIG. 4 is a block diagram showing one embodiment of the device according to the present invention, and FIG. Figures (al to (di) are waveform diagrams showing waveforms at each point of the device in Figure 4. ■...Low pass filter (delay means), 4...Bypass filter, 5...Noise amplifier with AGC , 6...
・Monostable multivibrator, 7... Subtraction circuit (arithmetic circuit), 8.9... Level hold circuit, 10...
Switch circuit (switch means) Patent applicant Pioneer Corporation (a) (C) Har1ruzu11 noise (b) ↑+ t2 Tohi1 High A in Ai Shigo (d)

Claims (1)

【特許請求の範囲】[Claims] 人力信号を遅延するための遅延手段と、この遅延手段の
出力信号及びこの出力信号中のパイロット信号をキャン
セルするためのパイロットキャンセル用信号がそれぞれ
入力される演算回路と、前記入力信号中のパルス性ノイ
ズを検出して一定幅のパルス信号を発生するノイズ検出
部と、前記出力信号及びパイロットキャンセル用信号が
加えられる入力端子と逆相の前記演算回路の入力端子と
アース間に交流的に接続され、通常オンしていて前記ノ
イズ検出部からのパルス信号に応じてオフするスイッチ
手段と、このスイッチ手段のオフしている間、前記遅延
手段の出力信号及びパイロットキャンセル用信号を前記
演算回路の前記逆相入力端子にそれぞれ伝達するレベル
ホールド回路とを備えることを特徴とするパルス性ノイ
ズ抑圧装獣。
a delay means for delaying a human signal; an arithmetic circuit to which an output signal of the delay means and a pilot cancellation signal for canceling a pilot signal in the output signal are respectively input; and a pulse characteristic in the input signal. A noise detection section that detects noise and generates a pulse signal of a constant width, and an input terminal of the arithmetic circuit having a phase opposite to the input terminal to which the output signal and the pilot cancellation signal are applied are connected in an alternating current manner between the ground and the input terminal of the arithmetic circuit. , switch means which is normally on and turned off in response to a pulse signal from the noise detection section; and while the switch means is off, the output signal of the delay means and the pilot cancellation signal are transmitted to the output signal of the arithmetic circuit. A pulse noise suppression device characterized by comprising a level hold circuit that transmits data to each negative phase input terminal.
JP19171581A 1981-12-01 1981-12-01 Suppressing device of impulsive noise Granted JPS5894242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19171581A JPS5894242A (en) 1981-12-01 1981-12-01 Suppressing device of impulsive noise

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19171581A JPS5894242A (en) 1981-12-01 1981-12-01 Suppressing device of impulsive noise

Publications (2)

Publication Number Publication Date
JPS5894242A true JPS5894242A (en) 1983-06-04
JPS6312409B2 JPS6312409B2 (en) 1988-03-18

Family

ID=16279268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19171581A Granted JPS5894242A (en) 1981-12-01 1981-12-01 Suppressing device of impulsive noise

Country Status (1)

Country Link
JP (1) JPS5894242A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01254412A (en) * 1988-04-01 1989-10-11 Okamoto Ind Inc Manufacture of antiskid net of tire

Also Published As

Publication number Publication date
JPS6312409B2 (en) 1988-03-18

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