JPS5893337A - Selecting method for semiconductor chip - Google Patents

Selecting method for semiconductor chip

Info

Publication number
JPS5893337A
JPS5893337A JP19334481A JP19334481A JPS5893337A JP S5893337 A JPS5893337 A JP S5893337A JP 19334481 A JP19334481 A JP 19334481A JP 19334481 A JP19334481 A JP 19334481A JP S5893337 A JPS5893337 A JP S5893337A
Authority
JP
Japan
Prior art keywords
tape
chips
perforated
adhesive tape
defective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19334481A
Other languages
Japanese (ja)
Inventor
Tadao Takano
高野 忠夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Rectifier Corp Japan Ltd
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp Japan Ltd
Infineon Technologies Americas Corp
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp Japan Ltd, Infineon Technologies Americas Corp, International Rectifier Corp USA filed Critical International Rectifier Corp Japan Ltd
Priority to JP19334481A priority Critical patent/JPS5893337A/en
Publication of JPS5893337A publication Critical patent/JPS5893337A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To shorten the select time of acceptables or defectives by a method wherein perforations are formed on a perforated tape according to the information in case of the measurement of electric characteristics, the perforated tape is conformed and stacked to a dividing pattern and an adhesive tape is glued onto the perforated tape. CONSTITUTION:Special form chips 12 and defective chips 13 are marked 14 in a probing process. The perforated tape 15 is perforated 16 while being made correspond to the pattern of marking 14 by means of a punching machine as well as the marking 14. The perforated tape 15 is stacked onto the surface of a semiconductor wafer 10 to which dicing is executed while being conformed to the dividing pattern, and the adhesive tape 17 is glued onto the perforated tape. When exfoliating the tape, only special form chips and defective chips are left on the adhesive tape, and acceptables or defectives can be selected for separation.

Description

【発明の詳細な説明】 法に係る。[Detailed description of the invention] Pertaining to law.

半導体チップの良品、不良品の選別を行なうには、一般
にウエノ・の状態でプロービングし、良品、不良品のマ
ーク付け7行なった後、ダイシングを施し、個々のチッ
プに分割して前記マークをたよりに選別を行なっている
In order to sort semiconductor chips into good and defective ones, generally, they are probed in a dry state, marked 7 times for good and defective chips, and then diced and divided into individual chips based on the marks. We are conducting a selection process.

かかる選別工程は、手作業で行なう場合あるいは自動ソ
ータ等の機械を使用する場合があるが、前者は、作業時
間がかかり、必然的に製品コストの高揚を免れない。
This sorting process may be performed manually or by using a machine such as an automatic sorter, but the former takes time and inevitably increases product costs.

また、後者の場合にも自動ソータ等の機械は、一般に、
良品ケ被選別物として選別を行なうためにその数が多く
未だ十分に選別時間の短縮を図ることができない。
Also, in the latter case, machines such as automatic sorters generally
Because good quality items are to be sorted, there are a large number of them, and it is still not possible to sufficiently shorten the sorting time.

両者の共通な工程としてブローピング工程後、半導体ウ
ェハを粘着テープに貼着する工程Y有するが、良品、不
良品の区別なく全体的に貼着されてしまうために、特に
良品に対する薬品洗浄工程を必要とすること及び粘着テ
ープからの剥離作業に多大な労力と時間を要し、かつ破
損等の危険性が高いこと等で問題があった。
A common process for both is the process of attaching the semiconductor wafer to an adhesive tape after the blotting process, but since the entire product is attached without distinction between good and defective products, a chemical cleaning process is especially necessary for non-defective products. There have been problems in that it requires a lot of effort and time to remove from the adhesive tape, and there is a high risk of breakage.

本発明は、上記の事情に基づいてなされたもので、半導
体ウェハの状態でプロービングすると同時にその電気的
特性測足時の情報にしたがい除去すべき異形チップ及び
不良テップに対応させて紙などの穿孔テープに穿孔を形
成し、ダイシング後このテープを上記半導体ウェハの分
割パターンに合せて重ね合せ、その上から粘着テープを
粘着させ、異形テップ及び不良チップのみ表前記紙テー
プの穿孔を介して粘着させて分離するとhv特徴とする
半導体チップの選別方法を提供する。
The present invention has been made based on the above-mentioned circumstances, and at the same time when a semiconductor wafer is probed, a paper or the like is punched in correspondence with irregularly shaped chips and defective tips to be removed according to information obtained when measuring the electrical characteristics of the semiconductor wafer. Perforations are formed in the tape, and after dicing, the tapes are stacked in accordance with the dividing pattern of the semiconductor wafer, and adhesive tape is applied from above, and only irregularly shaped chips and defective chips are adhered to the surface through the perforations in the paper tape. Provided is a method for sorting semiconductor chips that exhibit hv characteristics when separated.

以下に、本発明の一実施例を図面!参照して説明する。Below is a drawing of an embodiment of the present invention! Refer to and explain.

本発明は、第1図に示す工程を経て実施される。The present invention is carried out through the steps shown in FIG.

すなわち、あらかじめ接合部を作り込んだ半導体ウニハ
ケプロービング工程1によりプロービングする。
That is, probing is carried out by a semiconductor porcelain brush probing step 1 in which a bonding portion is created in advance.

同時に、ブロービング時の情報に基き除去すべき異形チ
ップ及び不良チップに対応する穿孔テープ上の位置にパ
ンチング2な行ない穿孔を形成す次いで、半導体ウニ/
lダイシング3を施した後、テープ貼り付は工程4に移
行する。
At the same time, punching 2 is performed to form holes on the perforation tape at positions corresponding to irregularly shaped chips and defective chips to be removed based on the information at the time of blobbing.
1 After performing dicing 3, tape attachment moves to step 4.

このテープ貼り付は工程では、前記の穿孔テープと半導
体ウェハの分割パターンと合致させた後前記テープ上に
粘着テープな貼着する。この時、粘着テープは、穿孔テ
ープの穿孔ン介して除去すべき半導体ウェハ上に貼着さ
れる。
This tape is attached in a process in which the perforated tape is made to match the division pattern of the semiconductor wafer, and then an adhesive tape is attached onto the tape. At this time, the adhesive tape is pasted onto the semiconductor wafer to be removed through the perforations of the perforated tape.

次に、ローラ等を転動させて、半導体ウニノーV個々の
チツ7vc分割5し、さらにテープ剥離6を行ない、最
終的に良品、不良品のチップ選別7を行なう。
Next, a roller or the like is rolled to divide the chips 7vc into individual chips 5 of the semiconductor unit V, and further tape peeling 6 is performed, and finally chips are sorted 7 into good and defective products.

この場合、異形チップ及び不良チップは、粘着テープ上
に残存し゛、きわめて容易に一良品選別ン行なうことが
できる。
In this case, irregularly shaped chips and defective chips remain on the adhesive tape and can be very easily screened out.

上記方法の要部をさらに詳述すれば以下の通りである。The main parts of the above method will be explained in more detail as follows.

1:′、。1:′,.

すなわち、たとえば第2図に示すように半導体ウェハ1
0から微細な角チップ11を形成する場合、ブロービン
グ工程において、異形チップ】2及び不良チップ13に
マーク付け14を行なっておく。
That is, for example, as shown in FIG.
When forming fine square chips 11 from 0, markings 14 are performed on irregularly shaped chips 2 and defective chips 13 in the blobbing process.

このマーク付け14と同時に同期して駆動されるパンチ
ング工程ジ(図示せず)KJ:す、紙などの薄い穿孔テ
ープ15に前記マーク付け14のノ(ターンに対応させ
て穿孔16を行なう。なお、この穿孔]6の形状、大き
さは、特に限定されな℃・が、除去すべきチップ形状、
大きさに出来るだけ近い方が好ましい。
A punching process KJ (not shown) is driven synchronously with this marking 14. A punching process 16 (not shown) is performed on a thin perforated tape 15 made of paper or the like in correspondence with the turns of the marking 14. , the shape and size of the perforation]6 are not particularly limited, but the shape and size of the chip to be removed
It is preferable that the size be as close as possible.

次いで、ダイシングを施した半導体ウニ/110の表面
に第4図に示すように穿孔テープ】5!分割パターンに
合せて重ね合せた後、穿孔テープ上に粘着テープ17を
貼着する。
Next, a perforated tape is applied to the surface of the diced semiconductor sea urchin/110 as shown in FIG. 4]5! After superimposing them according to the division pattern, adhesive tape 17 is stuck on the perforated tape.

この場合、穿孔テープ】5は、紙などの薄い材料で形成
されているために粘着テープ】7が穿孔】6乞通′して
除去すべき異形チップ及び不良チップの部分に貼着され
る。
In this case, since the perforated tape [5] is made of a thin material such as paper, the adhesive tape [7] is affixed to the portions of irregularly shaped chips and defective chips that are to be perforated and removed.

しかして、前記工程ン経てテープ剥離を行なえば、異形
チップ及び不良チップのみが粘着テープ上に残り、良品
、不良品を選別することができる。
If the tape is peeled off after the above steps, only irregularly shaped chips and defective chips will remain on the adhesive tape, allowing the selection of good and defective chips.

以上のように、本発明によれば異形チップ及び不良チッ
プを一個毎に除去していくものと異なり穿孔テープを通
してそれらヲー4工程で除去し得るよ□うにしたので、
良品、不良品の選別時間が著しく短縮される。
As described above, according to the present invention, instead of removing irregularly shaped chips and defective chips one by one, they can be removed in four steps through perforated tape.
The time for sorting between good and defective products is significantly reduced.

さらに、良品チップには、粘着テープが接着されないの
で、後の洗浄工程での洗浄時間が短縮でキ、かつ電気的
特性上、好ましから門る影響をさけることができる。
Furthermore, since the adhesive tape is not adhered to the non-defective chips, the cleaning time in the subsequent cleaning process can be shortened, and it is possible to avoid adverse effects on electrical characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1本発明ン実施するための工程図、第2図は、
ブロービング工程ン経た半導体ウエノ・の平面図、第3
図は、パンチング工程を経た穿孔テープの平面図、第4
図は、上記半導体ウエノ・、穿孔テープ及び粘着テープ
を順次、重ね合せた状態の断面図である。 10・・・半導体ウェハ、1】・・・角チップ、】2・
・・異形チップ、13・・・不良チップ、14・・・マ
ーク付け、15・・・穿孔テープ、17・・・粘着テー
プ。 出願代理人 弁理士 菊 池 五 部 第 l 図 第 2 園
Figure 1 is a process diagram for carrying out the invention, Figure 2 is a process diagram for implementing the invention.
Top view of semiconductor wafer after blowing process, 3rd
The figure is a top view of the perforated tape after the punching process.
The figure is a sectional view of the semiconductor wafer, perforated tape, and adhesive tape sequentially stacked one on top of the other. 10...Semiconductor wafer, 1]...Square chip, ]2.
... Irregular chip, 13... Defective chip, 14... Marking, 15... Perforated tape, 17... Adhesive tape. Application agent Patent attorney Kikuchi Division 5 Part 1 Figure 2 Garden

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハ上のチップ部をプロービングする工程と、
この工程と同期させて異形チップ部及び不良チップ部に
対応する穿孔テープ上の位置に穿孔を形成するパンチン
グ工程と、前記ウェハ乞ダイシングする工程と、前記ウ
ェハ上の異形チップ部及び不良チップ部の位置と前記テ
ープの穿孔位置とY合致させて重ね合せ、さらに前記テ
ープ上に粘着テーブン貼着する工程と、前記ウェハな個
々のチップに分割する工程と、前記粘着チー1剣離する
工程とを有し、前記粘着テープ上に異形チップ及び不良
チップのみ乞残存ヤせることン特徴とする半導体チップ
の選別方法。
a step of probing a chip portion on a semiconductor wafer;
In synchronization with this step, there is a punching step of forming perforations on the perforated tape at positions corresponding to the irregularly shaped chip portions and defective chip portions; a step of dicing the wafer; A step of overlapping the tapes in a Y-aligned position with the perforation position of the tape, further adhering an adhesive tape onto the tape, a step of dividing the wafer into individual chips, and a step of separating the adhesive tape by one piece. A method for sorting semiconductor chips, characterized in that only irregularly shaped chips and defective chips are left on the adhesive tape.
JP19334481A 1981-11-30 1981-11-30 Selecting method for semiconductor chip Pending JPS5893337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19334481A JPS5893337A (en) 1981-11-30 1981-11-30 Selecting method for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19334481A JPS5893337A (en) 1981-11-30 1981-11-30 Selecting method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPS5893337A true JPS5893337A (en) 1983-06-03

Family

ID=16306331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19334481A Pending JPS5893337A (en) 1981-11-30 1981-11-30 Selecting method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPS5893337A (en)

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