JPS59215739A - Sorting of semiconductor device - Google Patents
Sorting of semiconductor deviceInfo
- Publication number
- JPS59215739A JPS59215739A JP9091483A JP9091483A JPS59215739A JP S59215739 A JPS59215739 A JP S59215739A JP 9091483 A JP9091483 A JP 9091483A JP 9091483 A JP9091483 A JP 9091483A JP S59215739 A JPS59215739 A JP S59215739A
- Authority
- JP
- Japan
- Prior art keywords
- chips
- semiconductor
- semiconductor element
- rejected
- sorting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置の選別方法に関する。[Detailed description of the invention] The present invention relates to a method for selecting semiconductor devices.
従来、半導体基板上に能動、受動容素子からなり形成さ
れた半導体素子チップの機能良否選別に於て機能が満足
でない不合格半導体素子チップには、例えばインカーで
目印をつけておく。これを各半導体素子チップごとに切
断し、不合格半導体素子チップをピンセットで除去して
いる。しかしこれは作業性が悪く多大な時間と工数がか
かる。Conventionally, in functional quality screening of semiconductor element chips formed of active and passive capacitance elements on a semiconductor substrate, rejected semiconductor element chips with unsatisfactory functionality are marked with, for example, an inker. This is cut into individual semiconductor element chips, and rejected semiconductor element chips are removed with tweezers. However, this method has poor workability and requires a large amount of time and man-hours.
本発明は上記に示した従来技術の欠点をなくすため、検
査工程に於て機能が不合格となった半導体素子チップに
強磁性体人りインキで構成したマーキング剤を用いて印
をつけ、磁性反応を利用しこれを磁気的に摘出して、選
別を簡易にし、作業性を向上させることが可能な半導体
装置の選別方法を提供するものである。In order to eliminate the above-mentioned drawbacks of the prior art, the present invention marks semiconductor chips whose functionality has failed in the inspection process using a marking agent made of ferromagnetic ink, and The present invention provides a method for sorting semiconductor devices, which makes sorting easier and improves workability by magnetically extracting semiconductor devices using reactions.
上記目的を達成する為１本発明は半導体基板上に形成さ
れた能動、受動素子からなる多数の半導体素子チップを
検査し、不合格となったチップに磁気選別用マーキング
剤を用いてマーキングし、その後ウェハーを各チップ毎
に切断し、前記マーキングしたチップを磁石で選び出す
半導体装置の選別方法である。In order to achieve the above object, the present invention inspects a large number of semiconductor element chips consisting of active and passive elements formed on a semiconductor substrate, and marks rejected chips using a marking agent for magnetic selection, This is a semiconductor device sorting method in which the wafer is then cut into individual chips and the marked chips are selected using a magnet.
以下本発明を図面にもとづいて詳しく説明する。The present invention will be explained in detail below based on the drawings.
第１図の１は半導体素子チッ、プのひとつであυ、２は
前記半導体素子チップＩＫ不合格の目印としてつけた強
磁性体入りマーキング剤である。第２図は半導体基板上
に多数の半導体素子チップが形成されている図であり、
各々の半導体素子チップの電気的特性検査を行い不良と
なった場合は該不良チップ表面に強磁性体入シインキを
被着せしめる。第３図は例として半導体素子チップ１の
良品チップ４．不良品チップ３を示している。斜線のチ
ップは不良チップ３を示し該インキが被凋している。第
５図は本発明のシステムの流れを示す一実施例である。In FIG. 1, 1 is one of the semiconductor chip chips, and 2 is a marking agent containing a ferromagnetic material, which is used as a mark of failure of the semiconductor chip IK. FIG. 2 is a diagram showing a large number of semiconductor element chips formed on a semiconductor substrate.
The electrical characteristics of each semiconductor element chip are inspected, and if the chip is found to be defective, a ferromagnetic material-containing ink is applied to the surface of the defective chip. FIG. 3 shows, as an example, a good chip 4 of the semiconductor element chip 1. A defective chip 3 is shown. Diagonally shaded chips indicate defective chips 3, and the ink has faded. FIG. 5 is an embodiment showing the flow of the system of the present invention.
各半導体素子の機能を検査機１２を用いて行い不合格半
導体素子チップ３にマーキング装［１３でマーキング剤
をつける。このマーキング剤に強磁性体人シインキを用
いる。このると半導体基板を切断機１４で半導体素子チ
ップ毎に切断分離して第４図に示す半導体素子チップ１
０にしたあと合格半導体素子チップ４．不合格半導体素
子チップ３をそれぞれベルト１１にのせ移送し磁石８で
不合格半導体素子チップ３を選び除去する。The function of each semiconductor element is checked using an inspection machine 12, and a marking agent is applied to the rejected semiconductor element chip 3 using a marking device [13]. A ferromagnetic ink is used for this marking agent. Then, the semiconductor substrate is cut and separated into semiconductor element chips by the cutting machine 14, and the semiconductor element chips 1 shown in FIG.
4. Passed semiconductor element chip after setting it to 0. Rejected semiconductor element chips 3 are each placed on a belt 11 and transferred, and the rejected semiconductor element chips 3 are selected and removed using a magnet 8.
以上のごとく、本発明による選別方法によれは従来のピ
ンセットによる選別作業よりも数段に作業能率アップと
なり効果があるものである。As described above, the sorting method according to the present invention is more efficient and effective than sorting work using conventional tweezers.
第１図は半導体素子チップの斜視図、第２図は検査前の
ウェハー及び半導体素子群を示す平面図、第３図は検査
後強磁性体人シインキを付けた不合格チップと合格チッ
プが混在している切断後のウェハーの平面図、第４図は
本発明を実施する際に用いた一実施例を示す選別装置を
示す図、第５図は本発明を組み込んだ生産ラインの一実
施例を示す図である。
なお図において、１．１０・・・・・・半導体素子チッ
プ、２・・・・・・強磁性体入りマーキング剤、３・・
・・・・不合格半導体素子チップ、４・・・・・・合格
半導体素子チップ、８・・・・・・磁石、１２・・・・
・・検査機、１３・・・・・・マーキング装置、１４・
・・・・・切断機、１１・・・・・・ベルトである。
第１３
第７区
第３図Figure 1 is a perspective view of a semiconductor element chip, Figure 2 is a plan view showing a wafer and semiconductor element group before inspection, and Figure 3 is a mixture of rejected chips with ferromagnetic markings and passed chips after inspection. FIG. 4 is a plan view of a wafer after cutting, FIG. 4 is a diagram showing a sorting device showing an embodiment of the present invention, and FIG. 5 is an embodiment of a production line incorporating the present invention. FIG. In the figure, 1.10...semiconductor element chip, 2...marking agent containing ferromagnetic material, 3...
...Rejected semiconductor element chip, 4... Acceptable semiconductor element chip, 8... Magnet, 12...
...Inspection machine, 13... Marking device, 14.
. . . Cutting machine, 11 . . . Belt. 13th Ward 7 Figure 3
Claims (1)
の半導体チップを電気的に測定し、良否判別を行う半導
体装置の選別方法において、不良チップ上に強磁性体人
シインキを塗布し、該半導体基板を各チップに切断分離
し、該不良チップを磁気的に選別除去することを特徴と
する半導体装置の選別方法。In a semiconductor device sorting method that electrically measures a large number of semiconductor chips consisting of active and passive elements formed on a semiconductor substrate to determine pass/fail, a ferromagnetic ink is applied to the defective chip and the semiconductor 1. A method for sorting semiconductor devices, comprising cutting and separating a substrate into individual chips, and magnetically sorting out and removing the defective chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9091483A JPS59215739A (en) | 1983-05-24 | 1983-05-24 | Sorting of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9091483A JPS59215739A (en) | 1983-05-24 | 1983-05-24 | Sorting of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59215739A true JPS59215739A (en) | 1984-12-05 |
Family
ID=14011677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9091483A Pending JPS59215739A (en) | 1983-05-24 | 1983-05-24 | Sorting of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59215739A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596223A (en) * | 1993-12-16 | 1997-01-21 | Nec Corporation | Semiconductor device and method of selecting the same |
| KR100637590B1 (en) | 2005-07-08 | 2006-10-23 | 주식회사 탑 엔지니어링 | Apparatus for cutting glass substrates in manufacturing process of flat type displayer |
| WO2006119724A1 (en) * | 2005-05-12 | 2006-11-16 | Infineon Technologies Ag | Semiconductor chips for tag applications, devices for assembling the semiconductor chips and assembly method |
-
1983
- 1983-05-24 JP JP9091483A patent/JPS59215739A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596223A (en) * | 1993-12-16 | 1997-01-21 | Nec Corporation | Semiconductor device and method of selecting the same |
| WO2006119724A1 (en) * | 2005-05-12 | 2006-11-16 | Infineon Technologies Ag | Semiconductor chips for tag applications, devices for assembling the semiconductor chips and assembly method |
| US7922093B2 (en) | 2005-05-12 | 2011-04-12 | Infineon Technologies Ag | Semiconductor chips for TAG applications, devices for mounting the same, and mounting method |
| KR100637590B1 (en) | 2005-07-08 | 2006-10-23 | 주식회사 탑 엔지니어링 | Apparatus for cutting glass substrates in manufacturing process of flat type displayer |
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