JPS5893298A - Multilayer circuit board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring metallization construction method in a multilayer wiring board.

The first method for manufacturing thin film multilayer wiring boards that has been conventionally implemented is
This will be explained with reference to the figure and Fig. 2.

FIG. 1 is a flow sheet explaining the conventional manufacturing process of a wiring board, and FIG. 2 is a cross-sectional view for explaining each process.

In Figures 1 and 2 on page 2, A to J indicate each step.

First, after cleaning the first substrate, a glazed ceramic substrate generally used for thin film circuits, a film 2 of Ag is formed by vacuum evaporation or sputtering method, and then the M
Form a resist film 3 on the film by photoprocessing Q3)
Then, the resist film 3 is removed by an ordinary method to form a U wiring pattern by etching with a phosphoric acid-based etchant. This is done by uniformly forming polyimide resin by spin coating, pre-baking at about 200°C, and then curing in N2 at 350°C. Next, a resist film 3 is formed on the insulating layer 4 by photoprocessing in the same manner as described above, and then a connecting through hole 6 is formed using an etchant made of a mixture of hydrazino and ethylenesoamine (G). After removing the resist film, The polyimide insulating layer 4 is again baked in N2 at about 350°C.

In this way, the M wiring conductor layer 2 is formed on the substrate 1, and the connection through holes 6 are formed in the insulating layer 4 above it. Here, the AA oxide coating inside the through hole 6 is removed using a sulfamino acid etchant, and then light etched using a phosphoric acid etchant. After that, A9 (or Ni-Cr/c, C1/.□, etc.) is used as the second conductor layer.
5 is formed by vacuum evaporation or sputtering method as described above (J).

In this way, conventionally, a pretreatment step (I) is provided before forming the upper conductor layer 5, but as described above, this is to remove Ag and oxide coating 7 in the through hole 6.
If this is omitted, the connection resistance value of through hole 6 will be several Ω.
/ hole ~ number - 〇 / hole and an abnormally high number of holes occur, reducing the product yield υ
This is because it was the biggest factor inhibiting the

By performing the pretreatment step (I), the connection resistance value of the through hole 6 was significantly reduced to about several Ω/hole, but on the other hand, the AQ oxide coating was Not only the film &-1 but also the formed metal part was removed, and there was a step in the through hole 6 "r'r '+11"
! l:(2!Ili (2)), and after the formation of the upper conductor layer 5, wire breakage and cracks occur at the through-hole portion, reducing the wiring strength and causing a new factor that lowers the product yield. .

The present invention improves the prior art as described above, and provides a multilayer wiring board that can omit the pretreatment process using sulfamic acid and phosphoric acid etchants, and can reduce the connection resistance value at the through-hole portion. That is.

In order to achieve the above-mentioned object, the present invention provides a lower conductor layer of a thin film multilayer wiring board in which the main conductor portion is not made of M.
In addition, the opening in the insulating layer is covered with Au.

Next, an embodiment of the present invention will be described with reference to FIGS. 3 and 4.

FIGS. 3 and 4 are flow sheets corresponding to FIGS. 1 and 2 explaining the conventional example, and explanatory cross-sectional views of the process.

In FIGS. 3 and 4, the differences from FIGS. 1 and 2 explaining the conventional embodiment are the formation of the AI/Au film in the step 5 (g) and the formation of the Au4B wiring in the step 0, The only difference is that there is no pretreatment step CI), and the other steps are the same as in the previous embodiment, but the explanation of the other steps will be omitted, and only steps (G) and (O') will be explained.

In this embodiment as well, the substrate 1 is a glazed ceramic substrate 1 used for a thin film circuit, and after cleaning, a 1 μm M film is formed on the M film and 50 OA of Au is formed thereon by a vacuum film forming method such as vacuum evaporation or sputtering.

After forming the wiring conductor layer 2 in this way, a resist film 3 is formed, followed by a step of forming a first layer wiring pattern (in O', an iodine-based etchant is used for patterning A11,
A phosphoric acid etchant is used for patterning M. Thereafter, the removal of the resist and the formation of through holes are performed in the same manner as before, and the interlayer insulating film 4 constituting the multilayer wiring is formed using polyimide resin, and a new Ai! /Au (or Ni-Cr/)4
+ Cr/Cu) as described above. By repeating this process, two or more multilayer wiring circuits are constructed.

7r In the thin film multilayer wiring circuit constructed in this way, as shown in FIG.
It was confirmed that the connection resistance values of all μφ through holes could be reduced to 0.1Ω/hole or less.

The following table is a comparative light showing the specific effects of the multilayer wiring board according to the conventional method and the multilayer wiring board according to the present invention.

Table As shown in this table, with the conventional technology, the through-hole connection resistance value is large at several Ω/hole number of holes several Ω/hole, and the connection yield is 30%.
It was about. As a solution to this problem, by applying the pretreatment process (I), we were able to reduce the connection resistance value from 0.1Ω/hole to several Ω/hole, and the connection 7 100% yield was also improved to 80%. However, the wiring layer inside the υ through-hole was eroded by the M treatment, resulting in cracks and wire breaks. On the other hand, in the case of Kinei rJIC, the through holes are covered with Au, so even if the pretreatment process is omitted, the connection resistance value is 0.1Ω/hole. The yield could be improved to about 95 inches.

Note that a new Ai/A11 (or Ni-Cr/Au, Cr/C
It is also possible to form a multilayer wiring circuit with two or more layers by forming the wiring (e.g., U) as described above and providing through holes.

As described above, in the multilayer wiring board of the present invention, since the wiring conductor layer is coated with Au, the wiring conductor layer is not eroded during through-hole formation, and connections can be made even if the pretreatment process is omitted. The resistance value can be set to 0.1Ω/hole, and the connection yield can be greatly improved.

[Brief explanation of the drawing]

Figure 1 shows the manufacturing process of a conventional multilayer wiring board.
:: 'a8! 1,3291i (3) Flow sheet, FIG. 2 is an explanatory sectional view of each step, FIG. 3 is a flow sheet showing each step of the present invention, FIG. 4 is an explanatory sectional view of each step, and FIG. 5 is a graph showing the relationship between Au film thickness and connection resistance value. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Wiring conductor layer, 3... Resist film, 4... Insulating layer, 5... Second conductor layer, 6... Through pole 7... Oxide film. Agent Patent Attorney Tadashi Akimoto Figure 3 Figure 4

Claims (1)

[Claims] 1. In a thin film multilayer wiring board consisting of an insulating layer, an upper wiring layer of the insulating layer, and a lower wiring layer of the insulating layer connected through an opening in the insulating layer, the main conductor portion is used as the lower conductor wiring portion. υ is M, and the M wiring portion is coated with Au at least in the opening. 2. The multilayer wiring board according to claim 1, characterized in that two or more layers use AM wiring portions in which openings in the insulating layer are covered with Au.