JPS5890853A - Input detection circuit - Google Patents

Abstract

PURPOSE:To increase the amount of information of input signals and to provide a new function to a digital system, by providing an intemediate level state in addition to high and low level states, and detecting also the intermediate level state. CONSTITUTION:An input signal In is given to a logical circuit 13 through two inverting type input buffer circuits 11, 12 having different threshold voltage state. The logical circuit 13 performs a prescribed logical operation. When the levels of the input signal In are VDD-VIH1, levels of low; high; high are obtained at outputs A, B, C of the circuit 13, and when the levels of the In are intermediate level of VIL1-VIH2, and VIL2-GND, high; high; low and high; low; high levels are obtained at the outputs A, B, C, allowing to discriminate the high; intemediate; low, three levels of the input signal In.

Description

DETAILED DESCRIPTION OF THE INVENTION This method is an input detection path for detecting input levels of three or more values.

The signals handled by normal digital V-stem are:
High level (Levels) of signals such as voltage or non-existence
,low level (0 level)
M) (Light data at 2 is Lebel and 0 level 21
1 level, and the voltage level of write data is constant voltage E.
When the voltage level is higher than EVIH, the data is set as a level, and when the voltage level is higher than the constant voltage VIL, the data is set as the θ level and written into the memory area ζ.

By the way, the above-mentioned write data is not directly written into the memory area 2, but is written through an input bumper circuit Bu consisting of an inverter as shown in stripes 1-(2.
This is a factor that indicates the state of the threshold voltage. The voltage level of the data given to this human buffer path BuE is VD
The range between D (predetermined electric potential) and VIH (: That is, this data is detected as a level, and the voltage level of the data is within the range between V and GND (@ earth potential) =
This data is detected as the θ level. The above voltage level V! There is a level difference between a and VII (this is called the general C two-threshold voltage). This is an undefined area (intermediate level) that does not occur.Conventionally, this intermediate level is not used.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide at least one intermediate level state between these inner level states in addition to the lower level state and the low level state, and to To provide an input detection path that can increase the amount of input signal information and add new fIA capabilities to the digital system C2 (2). .

An embodiment of this example will be described below with reference to the following figures. The third one is this blunt input detection circuit 111! This is a circuit configuration diagram of an embodiment, and shows a case where the state of the input signal In is detected as a high level state, a low level state, and one intermediate level state between these two level states. In is connected to the @ buried path IJ via two inverting input buffer circuits 11 and 12 with different threshold voltages.
(: given. This logic j!N path IJ is input from the outputs of the above two input buffer (b) paths 11 and 12, and the input signal In
When it detects that it is in a high level state (level state), the signal A, which is a low level (θ level), and the input signal I
Signal B becomes low level when it detects that n is in a low level state, and signal B becomes low level (=signal 0 when it detects that input signal In is in an intermediate level state between high level state and low level state). Output.

And the above-Coffee circuit IS is Doki☆Ka~^,mu.

To output C (2. The above two input buffers 1g1
The output of j311.12 is parallel (: given Nand (
NAND) gate circuit 14, two inverters 1 that invert each output of the above two input puffer circuits 11 and 11.
5.16. The outputs of these two inverters 16.16 are given in parallel. U path 11, and a Nant gate circuit 18 to which the outputs of both the Nant gate circuits 14 and 17 are applied in parallel, and the Nant gate circuits 1F, 14. Each output signal of III is the above signal A.

B, CI = compatible.

FIG. 4 (1), (t)) is a diagram showing the state of the threshold voltage of the two input buffer circuits 11 and 11,
- Threshold l for high level input buffer circuit 11
1L output Vxu and low level threshold voltage VI
Since the input bumper circuit w112 of the other side is input buffer circuit W112, each of them is at a higher level than the level-sensitive threshold voltage VI)l and the low-level positive threshold voltage VIL.

In the above configuration, if the level state of the input signal In is in the range C2 between 62 VDD and Vral as shown by the broken line in the fifth factor, then ζ: is the two input buffers tj9Jl1511. The outputs of 12 are both I: high level, resulting in signals A and B.

As shown in FIG. 5, C becomes low level, high level, high level.

Next (if the level state of the two-power signal In is between are at a low level, and as a result, the signals A, B,
C is the 5th m + = as shown (- level, low level, Wb
The level state of the input signal In is indicated by the broken line in FIG.
(If there is 62, one input 3fufa 1g
The output of l path 11 is at a low level, and the other input buffer wj
1: The output of I becomes high level, and as a result, the signals A and B
, C is $51N (as shown in 2 (knee level).

High level, low level tonal.

That is, in this circuit, the level of the input signal vln is V
This level is detected as a high level between DD and VIHL, as a low level between VIL and GND, and as an intermediate level between VIL and Voil. Input signal In is 3
Having value data (2), compared to the conventional 2 (2), can increase the information it contains.

Figure #46 shows the (b) path factor when this invention is applied to a RAM (21a, Ilb in Figure 1).

JJC... is a single memory cell capable of writing and reading 6J data, and these memory cells are composed of two inverters xi, is and two transfer gates, as exemplified by one memory cell j7M). 21, Is
◎Each of these mesoricells J 1 a
, J 1 b, 21c... The other end of one transfer gate 24 is one pin) $I J #
The other end of the other transfer gate 25 is connected to the other transfer gate 1127, respectively, and both transfer gates in each memory cell are connected to each other. 4, the gate of II is N-
Each word @21a, l1lb, 21c l2 is connected. When data is written, the pits Hzi and xi are provided with the inverter 29 (: therefore, each of the complementary level 1: converted write data is given to the pits Hzi, xi, and both of the above bits are ≤2). zts, sr
In the middle of (= is the input detection circuit shown in FIG. The write data WD given to the inverter 29 or Visit@JF(:) is input as an input signal to the inverter 29 or visit@JF(:).

In such a RAM (2), when I1tC is at a low level, ζ- is both tri-state buffer Ig circuit 3o.

Jl is activated, and the selected word at this time)"+1
Memory cell 21i connected to 11741: The data of focus lines xi and zv are read. - When the coefficient C is at a low level, that is, when one level of the write data is at an intermediate level, both tristate buffer circuits so
, si do not operate and their output state becomes an impedance state, and no data is written to the memory cell 21≦= connected to the word fi1284 selected at this time. That is, in this RAM, write data is set at an intermediate level C2; thus, data writing can be controlled in -bit units.

! 1!7N is a 1gi path configuration diagram of another embodiment of the present invention. In the above embodiment, the state of the input signal In is
In addition to the low level state and the low level state (: This was a case where one intermediate level between these two level states was detected, but in this example circuit, JIKJII (a) to (e) - Three inverted manual buffer circuits 41, 41° 4J with different mutually different threshold voltages are provided, and the outputs of these manual buffer circuits are given as input signal 1nf) i% The signal JJ, M, F, and G corresponding to the two corresponding signals JJ, M, F, and G are made to be superior to each other in the form of a four-quadruple signal consisting of a level state, a low level state, and two intermediate levels between these two level states. By providing n @ manual buffer circuits with different voltages and applying the outputs of these input buffer circuits to the input circuit C2, a signal approximately corresponding to the (n+1) shape 11 of the input signal In can be obtained.

Moreover, the input detection (b) path according to the present invention C2 can be applied to various gage digital systems other than LAM, and by applying it to a digital system C2, new functions can be added.

Note that the present invention is not limited to the embodiment described above; for example, in the embodiment described above, the human-powered buffer circuit is of an inverting wet type; It's okay.

As explained above, C: According to this invention, 29 human-powered buffer circuits with different threshold values are provided for the input @, and the outputs of these human-powered buffer circuits are converted into logic [gIi
2i and this brass circuit 1: Therefore, for the above input signal, detect at least one intermediate level state between the level state and the low level state (from 2).
It is possible to provide an input detection circuit that can increase the information cover of an input signal and add a new function by using a digital V-stem (equalization).

[Brief explanation of drawings]

Figure 1 is a block diagram of the human-powered buffer circuit, Figure 2 is a diagram showing the state of its threshold voltage, and Figure 3 is a block diagram of the input detection (b) path of this invention (2). J (Jl)
, (b) is a diagram showing the relationship between the threshold voltages of the two input buffer (b) paths in the circuit of the above embodiment. Fig. 5 is a technical diagram showing the operation of the circuit of the above embodiment, Fig. 6 is a one-way configuration diagram of an application example of this example, and Fig. 7 is a (b) road diagram of Takeshi Sakaki of another embodiment of this invention. , Body 8-■ ~ (C) are factors that indicate the state of the threshold voltage of the three input buffers in the same example-route (= 11.11, 41.42.48... Inverted overflowing cover 7
7A M% IJ, 44... Theory j! Ig11118.1
4゜J7/, J#...su/)" (NA
NI)) Gate circuit, 15°16... Inverter, 2
1...Memory cell, z7t. 25, is...inverter, 74, Is...transformer gate, xi, 7F...bit line, 2
#...Word @, 10.81...Toki state buffer circuit. Izujin agent patent attorney Suzue Takehiko 1st-
Figure 2 Figure 3 (a) (b) Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] Create at least two input buffer paths whose threshold value is true for the input value ``f!
Discuss the output of the path! ! (Characterized in that the method is characterized in that two people are used to detect at least one intermediate level state between a high level state and a low level state of the input signal by means of a method (2) and a low level state of the input signal. Input detection 1gl road.