JPS5890092U - Inverter device - Google Patents

Inverter device

Info

Publication number
JPS5890092U
JPS5890092U JP15453182U JP15453182U JPS5890092U JP S5890092 U JPS5890092 U JP S5890092U JP 15453182 U JP15453182 U JP 15453182U JP 15453182 U JP15453182 U JP 15453182U JP S5890092 U JPS5890092 U JP S5890092U
Authority
JP
Japan
Prior art keywords
circuit
gate control
control circuit
inverter device
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15453182U
Other languages
Japanese (ja)
Other versions
JPS596158Y2 (en
Inventor
室山誠一
小林英敏
Original Assignee
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電信電話株式会社 filed Critical 日本電信電話株式会社
Priority to JP15453182U priority Critical patent/JPS596158Y2/en
Publication of JPS5890092U publication Critical patent/JPS5890092U/en
Application granted granted Critical
Publication of JPS596158Y2 publication Critical patent/JPS596158Y2/en
Expired legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案を適用するに適したパルス幅制御回路を
省略したパルス幅制御形インバータ装置のブロック構成
図、第2図は第1図の直流−交流変換部の回路例、第3
図は第1図のインバータ装置の出力電圧波形図、第4図
は第11図のインバータ装置に従来の停止手順を適用し
た場合の動作波形図、第5図は本考案の停止補償回路を
付加したインバータ装置の動作波形図、第一6図は本考
案の停止補償回路を付加した比較増幅回路の一実施例、
第7図は同じく本考案に係る停止補償回路を付加したゲ
ート制御回路部の他の実施例をそれぞれ示す。 1:直流入力端子、2:入力開閉器部、3:直流−交流
変換部、4:正弦化フィルタ、5:出力端子、6:ゲー
ト制御回路部、7:制御電源部、8:停止相、 全信号
入力端子、21:入力開閉器、22:直流フィルタ、6
1゛:比較増幅回路、62:電圧−位相変換回路、A:
停止補償回路。 I                        
     J             al  it −] 十 = ; : 、:。 目 1・、
FIG. 1 is a block diagram of a pulse width control type inverter device suitable for applying the present invention without a pulse width control circuit; FIG. 2 is a circuit example of the DC-AC converter shown in FIG. 1;
The figure is an output voltage waveform diagram of the inverter device in Figure 1, Figure 4 is an operating waveform diagram when the conventional shutdown procedure is applied to the inverter device in Figure 11, and Figure 5 is an illustration of the inverter device in Figure 11 with the addition of the stop compensation circuit of the present invention. The operating waveform diagram of the inverter device shown in FIG.
FIG. 7 shows another embodiment of a gate control circuit section to which a stop compensation circuit according to the present invention is added. 1: DC input terminal, 2: Input switch section, 3: DC-AC converter section, 4: Sine filter, 5: Output terminal, 6: Gate control circuit section, 7: Control power supply section, 8: Stop phase, All signal input terminals, 21: Input switch, 22: DC filter, 6
1゛: Comparison amplifier circuit, 62: Voltage-phase conversion circuit, A:
Stop compensation circuit. I
Jalit-] 10= ; : , :. Eye 1...

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] コンデンサ及びリアクタで構成される直流フィルタと入
力開閉スイッチを含む入力開閉器部、サイリスタをスイ
ッチング素子とし転流回路を備えた直流−交流変換部及
び正弦化フィルタを直列に接続し、比較増幅回路と電圧
−位相変換回路からな−るゲート制御回路を前記正弦化
フィルタの出力端子と直流−交流変換部間に接続し、前
記ゲート制御回路に制御電源部を接続してなるインバー
タ装置において、該インバータ装置を停止する際、前記
ゲート制御回路の出力パルス幅を細く絞るため、停止指
令信号により前記比較増幅回路の出力信号レベルを制御
するトランジスタ等よりなる停止補償回路を前記ゲート
制御回路の前記比較増幅回路に付加したことを特徴とす
るインバータ装置。
A DC filter consisting of a capacitor and a reactor, an input switch section including an input switch, a DC-AC converter section with a commutation circuit using a thyristor as a switching element, and a sine filter are connected in series to form a comparison amplifier circuit. An inverter device comprising: a gate control circuit comprising a voltage-phase conversion circuit connected between the output terminal of the sine filter and a DC-AC conversion section; and a control power supply section connected to the gate control circuit; When stopping the device, in order to narrow down the output pulse width of the gate control circuit, a stop compensation circuit consisting of a transistor or the like that controls the output signal level of the comparison amplifier circuit according to a stop command signal is connected to the comparison amplifier of the gate control circuit. An inverter device characterized by being added to a circuit.
JP15453182U 1982-10-14 1982-10-14 Inverter device Expired JPS596158Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15453182U JPS596158Y2 (en) 1982-10-14 1982-10-14 Inverter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15453182U JPS596158Y2 (en) 1982-10-14 1982-10-14 Inverter device

Publications (2)

Publication Number Publication Date
JPS5890092U true JPS5890092U (en) 1983-06-18
JPS596158Y2 JPS596158Y2 (en) 1984-02-24

Family

ID=29947127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15453182U Expired JPS596158Y2 (en) 1982-10-14 1982-10-14 Inverter device

Country Status (1)

Country Link
JP (1) JPS596158Y2 (en)

Also Published As

Publication number Publication date
JPS596158Y2 (en) 1984-02-24

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