JPS5889858A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the width of a polycrystal silicon fuse with high accuracy through a process shaping a stage difference section onto a substrate, a process forming a polycrystal silicon layer onto the substrate containing the stage difference section and a process removing the polycrystal silicon layer through anisotropic etching only by approximately the film thickness section. CONSTITUTION:A CVD oxide film 4 is grown onto a field oxide film 1, and the CVD oxide film 4 is obtained through selective ethcing. The polycrystal silicon layer 2 is grown onto the whole surface, and only by the film thickness section t2 is etched lest the polycrystal silicon layer 2 should remain on the whole surface of the polycrystal silicon layer 2 by a dry etcher having anisotropy in the whole surface. Since the actual film thickness t of the polycrystal silicon layer 2 is the sum of the thickness t2 of the grown film and the thickness of the CVD oxide film 4, stage difference t4, in the stage difference section of the CVD oxide film 4, the polycrystal silicon layer 2 remains in the film thickness of t4 along the stage difference of the CVD oxide film 4 when the polycrystal silicon layer 2 is ethced only by t2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a polycrystalline silicon fuse connected to a redundant bit of an insulated gate field effect type (hereinafter referred to as M2S type) memory circuit device. Regarding the method.

As the capacity of recent memory products increases, the memory cell occupancy rate also increases and the chip size also increases. Therefore, the memory play section is susceptible to the influence of dust during diffusion, and defects occur in the memory play section, making it difficult to obtain all bits of good quality. Therefore, it is effective to provide redundant or redundant columns to replace rows or columns containing such defects.

Here, Fig. 1 (al 4C polycrystalline silicon
Give an example. That is, 2-. A voltage is applied between 2' and a current is applied to cut the fuse. At that time, it is known that the power consumption P when the fuse blows is constant. The current flowing through the fuse is proportional to %WK, and the voltage applied between 2 and 2' is proportional to L.

Therefore, the following formula holds.

Since P=VIocWL=constant, it can be seen that the variation in l1cW and L determines the power consumption. Here, L is generally longer than WK, so the conditions for the optical achromatic method and the resist film thickness, etc.
μm) can be ignored. However, since wFi is short, the above-mentioned variation cannot be ignored, and it is proportional to wVi relaxation I. In other words, it can be seen that the variation in W greatly affects the power consumption P.

Therefore, it is necessary to precisely control the fuse W and L (W, which is minute in size to 4I).

As is well known, the conventional process for manufacturing fuses is carried out by a light exposure method in the process of forming polycrystalline silicon fuses. is W
There is a variation of 0.2 to 0.5 .mu.m in percentage, and it is currently difficult to form islands of 2 .mu.m or less with high precision. One object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates such conventional drawbacks.

The features of the present invention include, for example, the step of forming a C oxide film in the step of forming a polycrystalline silicon layer, the step of selectively removing the oxide film and forming a step in the oxide film, and the step of firstly forming a polycrystalline silicon layer on the entire surface. When growing a crystalline silicon layer and selectively removing a polycrystalline silicon layer, the polycrystalline silicon layer is grown and the polycrystalline silicon layer is selectively removed. A method for manufacturing a semiconductor memory circuit device, which includes a step of removing approximately the thickness of a silicon layer by an etching technique having total anisotropy, and uses the polycrystalline silicon layer remaining along the steps of the oxide film as a fuse. Niworu.

That is, the present invention provides a method for manufacturing an MO8 type memory circuit device, characterized in that the width W of a polycrystalline silicon fuse connected to a redundant bit is formed with high precision.

Next, embodiments of the present invention will be described with reference to the drawings.

Figure 2 (CVD on field oxide film l as shown in bl)
The oxide film 4 is grown and selectively etched using a photoetching technique to obtain the CVD oxide film 4.

Next, a polycrystalline silicon layer 2 is grown on the entire surface, and then the entire surface is etched using an anisotropic dry etcher (parallel plate type) so that no polycrystalline silicon layer 2 remains on the entire surface of the polycrystalline silicon layer 2. Only the film thickness t2 is etched.

Here, in the stepped portion of the CVD oxide film 40, the actual film thickness t of the polycrystalline silicon layer 2 is the grown film thickness t2 and the CVD oxide film 811.
4, that is, the sum of the step t4, so if the polycrystalline silicon layer 2 is etched by t2, as shown in FIG.
As shown in d, the polycrystalline silicon layer 2 remains along the step of the KCVD oxide film 4 with a thickness of %t4. What should be noted at this time is that w-tl and film thickness t4 depend only on etching and variations in the grown film thickness. Therefore, in etching having anisotropy in the etching plane, it is easy to determine the end point, and thus variations in the thickness of the grown film can be controlled with an accuracy of ±0.1 μm or less using known methods.

Therefore, the W and film thickness of the polycrystalline silicon fuse are ±0.1
It can be controlled with an accuracy of less than μm and fuses with good reproducibility can be obtained.

According to the present invention, since the width (W) and film thickness of the polycrystalline silicon wire are precisely controlled, the power consumption P of the polycrystalline silicon wire and wire is lower than that of the conventional photoetching method. It is possible to keep the variation small.

Although polycrystalline silicon has been described as the fuse material in the present invention, other fuse materials may be used.

It is amazing that similar effects can be obtained with W, Mo, Cr, etc., for example.

[Brief explanation of the drawing]

= Figure 1 (111~<O) is a plan view and a cross-sectional view of the conventional manufacturing process of a polycrystalline silicon layer, and Figure 1 (a)
Figure 1 (b) is a plan view of an example of a polycrystalline silicon fuse.
) * (c% is a cross-sectional view taken along line A-A' in FIG. 1(a). FIG. FIG. 2-(
i) is one plan view, and Fig. 2(b) and (C) are the second plan view.
FIG. 3 is a sectional view taken along line BB' in FIG. In the figure, %1...Field oxidation 1m
, 2...polycrystalline silicon layer, 3...
・Photoresist, 4...CVD oxide film.

Claims (1)

[Claims] A method for manufacturing a semiconductor device having a memory matrix including redundant rows or columns, comprising: providing a stepped portion on a substrate; and providing a polycrystalline silicon layer on the substrate with the stepped portion. . A method for manufacturing a semiconductor device, comprising the steps of: removing the polycrystalline silicon layer by approximately the thickness of the polycrystalline silicon layer by anisotropic etching.