JPS5887875A - Twin-gate type mis semiconductor device - Google Patents
Twin-gate type mis semiconductor deviceInfo
- Publication number
- JPS5887875A JPS5887875A JP18543881A JP18543881A JPS5887875A JP S5887875 A JPS5887875 A JP S5887875A JP 18543881 A JP18543881 A JP 18543881A JP 18543881 A JP18543881 A JP 18543881A JP S5887875 A JPS5887875 A JP S5887875A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- substrate
- drain
- source
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000003321 amplification Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 235000013351 cheese Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は双（チーアル）ゲート型ＭＩＳ半導体装置に関
する。以下、ＭＩＳ半導体装置をＭ■ＳＦ Ｅ Ｔと言
う。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual gate type MIS semiconductor device. Hereinafter, the MIS semiconductor device will be referred to as MSFET.
テレビジョンチューナ用高周波増幅用に使用される双ゲ
ート型ＭＩＳＦＥＴにおいては高性能化すなわち低雑音
化、低電圧動作化が要求されており、そのためにこのＭ
Ｉ Ｓ Ｆ １２ Ｔの低容１″化ど高順伝達アドミ
ッタンス化が必要となっている。Twin-gate MISFETs used for high-frequency amplification in television tuners are required to have higher performance, that is, lower noise and lower voltage operation.
It is necessary to lower the capacity of ISF 12T to 1" and increase the forward transfer admittance.
本願出願人において提案されているＮチャンネル双ゲー
ト型Ｍ Ｉ Ｓ Ｆ Ｅ Ｔは第１図に示すように、高
抵抗Ｐ型Ｓｉ（シリコン）基体１の主表面にＮ ４−型
ソース領域２及びＮ１型ドレイン領域３を形成し、ソー
ス・ドレイン間Ｓｉ 基体表面上にゲート絶縁膜（Ｓｉ
Ｏ，膜）４を介して第１ＭＯ（モリブデン）ゲートＧ１
及び第２Ｍｏゲート（矛、を形成し、ゲートの形成され
ないソース・ドレイン間８１基体表面に高耐圧部となる
Ｎ一層５ａ、５ｂ、５ｃを形成した構造を有する。とこ
ろで、このような構造のＭＩＳＦＥＴにおいて、低容１
化のために例えば第１ゲートＧ１のチャネル長β１を小
さくするとＣ１５ｓ（入力容量）を小さくできるが、そ
のためパンチスルーを起しやすくなることがわかった。As shown in FIG. 1, the N-channel dual-gate MISFET proposed by the applicant of the present invention has an N 4-type source region 2 and An N1 type drain region 3 is formed, and a gate insulating film (Si
first MO (molybdenum) gate G1 via O, film) 4
It has a structure in which a second Mo gate (spear) is formed, and N single layers 5a, 5b, and 5c, which serve as high breakdown voltage parts, are formed on the surface of the substrate 81 between the source and drain where no gate is formed.By the way, a MISFET with such a structure In, low volume 1
For example, C15s (input capacitance) can be made smaller by reducing the channel length β1 of the first gate G1, but it has been found that this makes punch-through more likely to occur.
これを防ぐためにチャネル部の不純物濃度を全体的に上
げるとＣｏ５５（出力容量）が大きくなることがわかっ
た。さらに、上記構造によれば順伝達アドミタンス（ｇ
ｍ）（ゲートの電圧変化分に対するドレイン電流の変化
分）が低くなり、低電圧（■Ｄ８：６■）では雑音指数
が大きくなり前記用途に使用で超ないことがわかり、又
Ｃｒ５ｓ（帰還容量）を小さくするためにゲートＧ、の
チャネル長ｐ、を大きくとると低性能化し、チャネル濃
度を高くするとドレイン側でＣｏ５５が大きくなるなど
の問題があることがわかった。It has been found that if the impurity concentration in the channel portion is increased overall to prevent this, Co55 (output capacitance) increases. Furthermore, according to the above structure, the forward transfer admittance (g
m) (change in drain current with respect to gate voltage change) becomes lower, and at low voltage (■D8:6■), the noise figure increases and it is found that it cannot be exceeded when used for the above purpose. ), it was found that increasing the channel length p of the gate G leads to lower performance, and increasing the channel concentration causes problems such as an increase in Co55 on the drain side.
本発明は上記した諸問題を解決するためσ）もσ）で、
その目的は高周波増幅用のＭ Ｉ Ｓ Ｆ Ｅ１’の高
性能化、腐信順性化にある。In order to solve the above-mentioned problems, the present invention has σ) and σ),
The purpose is to improve the performance and compliance of MISF E1' for high frequency amplification.
第２図は本発明によるＮチャネル双ゲート型ＭＩＳＦＥ
Ｔの原理的構造を示すものである。このＭＩＳＦＥＴが
第１図で示したこれまでのＭＩＳＦ Ｅ Ｔと鷲なる点
は、第１ゲートＧ、と第２ゲート〔）２の一部を含むソ
ース・ドし・７１ン間のＰｓｉ基体の表面に基体の不純
物濃度よりもＸ）＼′高い濃度のｌ〕型層６を高耐圧部
Ｎ−Ａ：１５ ａ 、 ５ ｂよりも深く形成したこと
に、゛し）る。Figure 2 shows an N-channel double-gate MISFE according to the present invention.
This shows the basic structure of T. The difference between this MISFET and the previous MISFET shown in FIG. The reason for this is that the 1] type layer 6 with a concentration X)\' higher than the impurity concentration of the substrate is formed on the surface deeper than the high breakdown voltage portions NA: 15a, 5b.
第３図（ａ ｌ〜ｌｄ）は上記第２図でｙＪ＜（、た”
−ｆｒ 不ルベゲー １、Ｍｉ ｓ ｔ；’ ト〕’ｒ
の製清ゾ■コｌニスなノ１り［２、以ド各−Ｌ程ごとに
具体的に説明する。Figure 3 (a l~ld) is yJ<(,ta''
-fr Furubegame 1, Mis t;'ト]'r
[2, each step will be explained in detail below.
ｆａｌ 低損ｌＷの１）−Ｓｉ基体１（不純物ｍＪｉ
Ｎ：ｌｏ”ａｔｏｍｓ／ｃ＋＋！程度）を用意し、図示
されないが保護ダイオードを形成後、表面に形成した厚
い酸化膜（Ｓｉｎ２膜）７をホトエッチ処理１７てこれ
をマスクとし、例えばＰ（リン）の高濃度Ｔポジット・
拡散によりソース及びドし・インとなるＮＦ領域２゜３
を形成する０、
（ｂｌ 次いでソース・ドレインを含めてその間のＳ
ｉ基体表面の酸化膜７を取り除き、ドレイン側の８ｓ基
体表面にホトレジスト膜によるマスク８を形成する。こ
のマスク８は同図（Ｃ）を診照し第２ゲートとなるべき
部分の一部を含む位置に形成する。こノ後、Ｂ（ボロン
）イオン打込み（Ｎ、１０ａｔｏｍｓ／ｃｉ程度）を行
ない、上記マスク８の形成されないＳｉ基体表面に基板
よりやや高い濃度の２層６を充分な深さく例えば１μｍ
）に形成する。この１層６形成は第１ゲー１−Ｇ、θ）
ノくンチスルー防止及び帰還容量Ｃｒ５ｓ低減のために
行なうものであり、この工程（ｂ）はこれまでのプロセ
スに対して新たに付加されたものである。fal Low loss lW 1)-Si substrate 1 (impurity mJi
After forming a protective diode (not shown), a thick oxide film (Sin2 film) 7 formed on the surface is photoetched 17, and this is used as a mask. High concentration T-posit
NF region 2゜3 which becomes source and drain/in due to diffusion
0, (bl then S between including the source and drain)
The oxide film 7 on the surface of the i-substrate is removed, and a mask 8 made of a photoresist film is formed on the surface of the 8s-substrate on the drain side. This mask 8 is formed at a position that includes a part of the portion to become the second gate, referring to FIG. After this, B (boron) ion implantation (N, about 10 atoms/ci) is performed to form a second layer 6 with a slightly higher concentration than the substrate on the surface of the Si substrate where the mask 8 is not formed, to a sufficient depth of, for example, 1 μm.
) to form. This one layer 6 formation is the first game 1-G, θ)
This step (b) is performed to prevent chip-through and reduce feedback capacitance Cr5s, and this step (b) is newly added to the previous process.
（ｃ） この後、ホトレジスト８を取り除き、熱酸化
によりソース・ドレイン間の８ｓ基体表面に薄い（５０
０〜１０００＾程度）ゲート酸化膜４を形成する。この
ゲート酸化膜形成は同時に工程（ｂ）でイオン打込みし
たＢの拡散と結晶のアニールをかねることになる。次い
で全面にゲート電極のためのＭｏ （モリブデン）を蒸
着又はスノくツタリングにより形成し、ホトエツチング
処理により、第１ゲートＧ１ 、第２ゲートＧ、及び図
示されない配線の一部を残して不要のＭｏを取除く。か
くして得られたＭＯゲート及び厚い酸化膜をマスクとし
て自己整合的に低濃度ＫＰ（ＩＪン）をイオン打込みし
く Ｎ ： １０” ａｔｏｍｓ ／ＣＴＩ程度）、ソ
ースとゲートＧ１間・ゲートＧｌ ・０２間、Ｊ とド
レイン間のＳｉ基板表面に高耐圧層とｌ「るＮ一層５ａ
。(c) After this, the photoresist 8 is removed and a thin layer (50
0 to 1000^) A gate oxide film 4 is formed. This gate oxide film formation simultaneously serves to diffuse the B ions implanted in step (b) and to anneal the crystal. Next, Mo (molybdenum) for the gate electrode is formed on the entire surface by vapor deposition or slatting, and unnecessary Mo is removed by photoetching, leaving the first gate G1, the second gate G, and a part of the wiring (not shown). remove. Using the thus obtained MO gate and thick oxide film as a mask, low concentration KP (IJ) is ion-implanted in a self-aligned manner (N: about 10" atoms/CTI) between the source and the gate G1 and between the gates G1 and 02. A high breakdown voltage layer and a single N layer 5a are formed on the surface of the Si substrate between the J and the drain.
.
５ｂ、５ｃを形成する。5b and 5c are formed.
（ｄ） 全面に層間絶縁膜９として例えばＣＶＤ、Ｓ
ｉｎ。(d) For example, CVD, S
in.
又はＰＳＧ（リン・シリケート・ガラス）等を形成し、
アニール処理により工程（Ｃ）でイオン打込みしたＰを
活性化した後、ソース・ドレイン部に対しコンタクトホ
トエッチを行ない、Ａｅ（アルミニウム）を蒸着、パタ
ーニングに」゛す、第２層目の配線となるＡ、６電極１
０を形成する。Or form PSG (phosphorus silicate glass) etc.
After activating the P ion-implanted in step (C) by annealing, contact photoetching is performed on the source and drain regions, and Ae (aluminum) is evaporated and patterned to form the second layer wiring. A, 6 electrodes 1
form 0.
上記プロセスで工程（ｂ）でＢイオン打込みを行なうこ
とにより、このＢ打込みを行わない場合はゲート長を少
なくとも２．２μｍを必要と［、だのに対し１．６μｍ
以下に短縮することになった。By implanting B ions in step (b) of the above process, the gate length needs to be at least 2.2 μm [, whereas it is 1.6 μm if B implant is not performed].
It has been shortened to the following.
以上実施例で説明した本発明によれば下記の理由で前記
発明の目的が達成できるとともに諸効果が得られる。According to the present invention described in the embodiments above, the object of the invention can be achieved and various effects can be obtained for the following reasons.
（１）ショートチャネル化（２，２ｆｉｍ−＋ １．６
μｍ ）ができ、しかもパンチスルーが起ら１．「い
ことで、ｌｍ伝達アドミッタンスが例えば４０％向−ヒ
する。(1) Short channelization (2,2fim-+ 1.6
μm), and punch-through occurs.1. ``As a result, the lm transfer admittance is increased by, for example, 40%.
（２）入力容ｉｉ Ｃｉ ｓ ｓは同等であるが、ゲー
トＧ２のチャネルのソース側寄りの一部へＢを打込んだ
ことにより帰還谷址ｃｒｓｓが２０％低減できた。(2) Although the input capacitance ii Ci s s is the same, the feedback valley crss can be reduced by 20% by implanting B into a part of the channel of the gate G2 near the source side.
（３）低容緻化により■Ｄ８−６Ｖでの雑音指数（ｆ＝
９００ＭＨ□）が４．２（ＩＢから３．２ ｄ Ｂと大
幅に改善された。(3) Due to low volume density ■Noise figure at D8-6V (f=
900MH□) was significantly improved to 4.2 (3.2 dB from IB).
本発明は低容量のＰチャネル及びポリシリコンゲートを
含む双ゲー１型Ｍ Ｉ Ｓ Ｆ １２１”一般に適用す
ることができ、・−？レビジョンチーーす用（ＶＨＦ高
周波増幅用）のトランジスタに利用して極めて有効であ
る。The present invention can be generally applied to dual-game 1 type MISF 121'' including low capacitance P-channel and polysilicon gates, and is extremely useful for use in transistors for revision cheese (VHF high frequency amplification). It is valid.
第１図はこれまでのタイプの双ゲートＭＩＳＦＥ ｉ’
の断面図、第２図は本発明による双ゲートＭＩ Ｓ Ｆ
ＥＴの断面図、第３図１ａ）〜ｆｄｌは本発明による
ヘチャネル双ゲ−） Ｍ Ｉ Ｓ Ｆ Ｅ ’ｌ”の製
造プロセスを下す要部工程断面図である。
Ｉ Ｐ−型Ｓｉ 基板、２・・Ｎ′ ソース、３− Ｎ
”ドレイン、４ ゲート絶縁膜、５ Ｎ一層、６・・
・Ｐ層、７・・酸化膜、８ ホトレジストマスク、９・
・層間絶縁膜、１０・・Ａｅ電極。
１．、、Ｑ 、、：
第 １ 図
第 ２ 図
？
’？ ？ｆｚ ？ＤFigure 1 shows the conventional type of twin-gate MISFE i'
FIG. 2 is a cross-sectional view of the twin-gate MISF according to the present invention.
The cross-sectional views of ET and FIGS. 3(a) to 3(fdl) are cross-sectional views of the main parts of the manufacturing process of the hechannel double-gauge according to the present invention.IP-type Si substrate, 2 ...N' sauce, 3-N
``Drain, 4 Gate insulating film, 5 N single layer, 6...
・P layer, 7.・Oxide film, 8 Photoresist mask, 9・
-Interlayer insulating film, 10...Ae electrode. 1. ,,Q,,: Figure 1 Figure 2? '? ? fz? D
Claims (1)
電型高濃度領域を形成してそれぞれをソース及びドレイ
ンとし、ソース・ドレイン間の半導体表面上に絶縁膜を
介して導体層からなる第１ゲート及び第２ゲートを形成
し、これら導体層の形成されないソース・ドレイン間の
半導体表面に第２導電型低濃度層を形成した双ゲート型
ＭＩＳ半導体装置において、ソースから第２ゲートにか
けて第２ゲート下の一部を含み半導体表面に基体の不純
物濃度よりもやや高い濃度の第１導電型層を前第２導電
型低濃度層よりも深く形成して成る双ゲート型ＭＩＳ半
導体装置。 ２、第２導電型半導体基体はＰ型シリコン基体であり、
ソース・ドレインとなる上記第２導電型高濃度領域はＮ
型である特許請求の範囲第１項に記載の双ゲート型ＭＩ
Ｓ半導体装置。[Claims] 1. High concentration regions of a second conductivity type spaced apart from each other are formed on the surface of a semiconductor substrate of a first conductivity type to serve as a source and a drain, respectively, and an insulating film is formed on the semiconductor surface between the source and drain. In a double-gate MIS semiconductor device in which a first gate and a second gate made of a conductor layer are formed via a conductor layer, and a second conductivity type low concentration layer is formed on the semiconductor surface between the source and drain where these conductor layers are not formed, A double layer formed by forming a first conductivity type layer with a slightly higher concentration than the impurity concentration of the substrate on the semiconductor surface from the source to the second gate, including a part under the second gate, and deeper than the second conductivity type low concentration layer. Gate type MIS semiconductor device. 2. The second conductivity type semiconductor substrate is a P-type silicon substrate,
The second conductivity type high concentration region which becomes the source/drain is N
The dual-gate type MI according to claim 1, which is a type
S semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18543881A JPS5887875A (en) | 1981-11-20 | 1981-11-20 | Twin-gate type mis semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18543881A JPS5887875A (en) | 1981-11-20 | 1981-11-20 | Twin-gate type mis semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5887875A true JPS5887875A (en) | 1983-05-25 |
Family
ID=16170785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18543881A Pending JPS5887875A (en) | 1981-11-20 | 1981-11-20 | Twin-gate type mis semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5887875A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250835A (en) * | 1991-01-16 | 1993-10-05 | Casio Computer Co., Ltd. | Field effect type thin film transistor having a plurality of gate electrodes |
| US5272369A (en) * | 1990-03-28 | 1993-12-21 | Interuniversitair Micro-Elektronica Centrum Vzw | Circuit element with elimination of kink effect |
| EP0585942A1 (en) * | 1992-09-03 | 1994-03-09 | Sumitomo Electric Industries, Ltd. | Dual gate MESFET |
| US5602501A (en) * | 1992-09-03 | 1997-02-11 | Sumitomo Electric Industries, Ltd. | Mixer circuit using a dual gate field effect transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50154074A (en) * | 1974-05-31 | 1975-12-11 | ||
| JPS50154075A (en) * | 1974-05-31 | 1975-12-11 | ||
| JPS5367373A (en) * | 1976-11-29 | 1978-06-15 | Hitachi Ltd | Semiconductor device |
| JPS5660060A (en) * | 1979-10-22 | 1981-05-23 | Hitachi Ltd | Mos semiconductor device |
-
1981
- 1981-11-20 JP JP18543881A patent/JPS5887875A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50154074A (en) * | 1974-05-31 | 1975-12-11 | ||
| JPS50154075A (en) * | 1974-05-31 | 1975-12-11 | ||
| JPS5367373A (en) * | 1976-11-29 | 1978-06-15 | Hitachi Ltd | Semiconductor device |
| JPS5660060A (en) * | 1979-10-22 | 1981-05-23 | Hitachi Ltd | Mos semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5272369A (en) * | 1990-03-28 | 1993-12-21 | Interuniversitair Micro-Elektronica Centrum Vzw | Circuit element with elimination of kink effect |
| US5250835A (en) * | 1991-01-16 | 1993-10-05 | Casio Computer Co., Ltd. | Field effect type thin film transistor having a plurality of gate electrodes |
| EP0585942A1 (en) * | 1992-09-03 | 1994-03-09 | Sumitomo Electric Industries, Ltd. | Dual gate MESFET |
| US5389807A (en) * | 1992-09-03 | 1995-02-14 | Sumitomo Electric Industries, Ltd. | Field effect transistor |
| US5602501A (en) * | 1992-09-03 | 1997-02-11 | Sumitomo Electric Industries, Ltd. | Mixer circuit using a dual gate field effect transistor |
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