JPS5886645A - Input and output controlling system - Google Patents

Abstract

PURPOSE:To facilitate program control, to reduce program capacity, and to prevent an overrun, by providing a specific interruption level and controlling it by programs with other interruption levels. CONSTITUTION:A microprocessor 1 has interruption levels. In a memory space 2, an interface area 7, FPD (floppy disk) controlling program 8, display controlling program 9, printer controlling program 10, ending processing program 11, and other various programs 12 are stored. In an IO space 3, an FPD controlling register group 13, display controlling register 14, printer controlling register group 15, and flip-flop 16 controllable by a program are stored. The flip-flop 16 is set by interruption processing programs with other interruption levels.

Description

Detailed Description of the Invention (11) Technical Field of the Invention The present invention relates to an input/output control method, and relates to an input/output control method for controlling 1% km of input/output devices by a single microprocessor. .

(2) Prior art and problems In the conventional input/output control method, the startup process of the input/output device, data transfer process, # ! The termination processing and asynchronous interrupt processing were being performed incorrectly. This type of conventional input/output control method requires completion processing for reporting completion to a higher-level program, reporting asynchronous interrupts, and asynchronous interrupt processing for each input/output device, making the control complex. was there. Furthermore, data transfer for low-priority input/output devices cannot be performed while high-priority input/output devices are being cleaned up, so there is a high possibility that an overrun will occur.

(3) Purpose of the invention The present invention obviates the above-mentioned drawbacks.

A specific interrupt level is used for finalization processing and asynchronous processing common to each input/output device, and a lip-flop is provided that can be controlled by programs at other interrupt levels as an interrupt source for that interrupt level. It is an object of the present invention to provide an input/output control method that can simplify program control, reduce program capacity, and prevent overruns. (4) Structure of the invention; Therefore, the input/output control method of the present invention is as follows.

In a data processing system having a microprocessor with multiple interrupt levels, a flip-flop that generates an interrupt request signal of a specific interrupt level is provided, and the flip-flop is used by another interrupt program. It is characterized by being able to be controlled.

(5) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 1 is a diagram showing a software configuration of an embodiment of the present invention, FIGS. FIG. 3 is a time chart showing conventional input/output processing, FIG. 4 is a time chart showing input/output processing according to the present invention, and FIG. , FIG. 6 is a diagram showing the software configuration of the second embodiment of the present invention.

In FIG. 1, 1 is a microprocessor, 2 is a memory space, 3 is an IO unit, 4 is a floppy disk device,
4 is a display device, 6 is a printer device, 7-digit interface area, 8uFPD (floppy disk) control, program, 9-digit display control program, printer control program, 11-digit final processing program, 12 is various programs. U-gram, J 3FiPPD control register group.

14 is a display control register, 15 is a printer control register group ijFPD termination flag area, 18 is a display termination flag area, and 19 is a printer termination flag area.

应 and Ti indicate interrupt request signal lines, respectively.

The microprocessor F1 has multiple interrupt levels.The memory space 2 includes an interface area 7. PP
I) Control program 8. Display control program 9
．． Printer control program 10゜Final processing program 1
1 and various other programs 12 are arranged. In IO space 13.

FPD control register #13. Display control register 14. A group of printer control registers 15 and a programmable flip-flop 116 are accommodated. Addresses are assigned to each register of FPD control control register group, display control register group 14, and printer control register group 5, 4, and the flip-flop.

Microprocessor 1 can access these various registers [3] and flip-flops.

FPD control control register group upper 3 is for controlling the Rotsubui disk device 4.

The display control register group 14 is a display device]
5, and the printer mt+ control tz
The register group 15 is the xth register that controls the printer device 6. An interrupt request line 1 or Ti is provided between the microprocessor 1 and each of a plurality of interrupt request flip-flops (not shown). An interrupt request line T1 is also provided between the flip-flop 16 and the microprocessor 1, and when the slip-flop 16 is set, the interrupt request signal on the signal line T becomes logic rlJ. .

Microprocessor l has multiple interrupt levels as described above. The non-interrupt level is the normal program execution level. The lowest interrupt level is assigned for cleaning up each input/output device and handling aperiodic interrupts. Other interrupt levels are assigned based on the data transfer priority of each output device.

Further, a flip-flop 16 is provided as an interrupt factor for the lowest level interrupt. This clip-flop 16 can be set by an interrupt processing program of another interrupt level.

Figures 2(a) and 2(a) show an example of the software configuration of one embodiment of the present invention.1 When a print command in a normal program is fetched, execution of the print control program is started. Ru. The print control program performs the following processing.

■ Check whether the printer is operable or not.

If possible, process (■) is performed, and if it is not possible, process (2) is performed.

■ Write the print specification on the printer device 6.

Return to normal program.

7' When an interrupt request is sent from the rt computer device 6.

The microprocessor 1 checks whether or not this interrupt request is accepted, and if it is accepted, it executes the interrupt processing routine in the printer control program. This interrupt processing routine performs the following processing.

■ Check whether printing has finished. If the answer is Yes, perform the process ``■'', and if the answer is No, perform the process ``■''.

■ Check the η island if it is the final data *If Yes, perform the process in ■; if No, perform the process in ■.

■ Transfer the print data to the printer device 6, and then return to the normal program.

■ Transfer the final print data to printer f6.

■ Command the printer to start and return to the normal program.

■ Store the end status in memo 17K.

(2) Turn on the termination flag in the printer termination flag area 19.

0 Sets the flip-flop 16 that causes the interrupt request signal; 1 Returns to the normal program.

Furthermore, what is the 1-interrupt request signal η?

This means the signal on the interrupt request signal line T1.

Microprocessor 1 interrupt request signal is logic “1”
”, interrupt level d is detected.
Check to see if there are high interrupt requests, and if not, run a cleanup program. The following processing is performed by executing the cleanup program.

■ Slip-flop that causes interrupt request signal T1] 6 to 0FFVct6゜ ■ Turn on the “end” flag for each device (input/output device)
[Suru 11 Yes, process Fio, then N.

Report any errors.

◎ Set the end flag of the corresponding device to 0FF.

While waiting for the O#x device to complete its operation, preparations are made to include part of the samurai program.

Oall') Is the end flag of the device ON?

Find out whether or not. If Yes, process [phase].

The mind returns to its normal program.

0 Turn on the flip 70 tube 16, which causes an interrupt request signal.

FIG. 3 is a time chart showing conventional input/output processing. Input/output processing is performed in the order of startup processing, data transfer, and termination processing.When a data transfer interrupt request is sent from interrupt level 1 while executing startup processing for an input/output device at interrupt level 0 and n. When this occurs, the activation process for the input/output device of 1 interrupt level n is interrupted, and data transfer to the input/output device of 1 interrupt level m is performed.

This interrupt request cannot be immediately accepted for termination processing for the input/output device of interrupt level m, but is deferred until the termination processing of interrupt level m is completed.

FIG. 4 is a time chart showing input/output processing according to the present invention. According to the present invention, part of the finalization process is executed at the lowest interrupt level. Therefore, if a data transfer interrupt request is received while the lowest interrupt level finalization process is being executed, or if there is a conflict between the lowest interrupt level interrupt request and the data transfer interrupt request, the data transfer interrupt request is immediately issued. is accepted and data transfer begins.

FIG. 5 is a diagram showing the hardware configuration of the second embodiment of the present invention. FIG. 6 is a diagram showing the software configuration of the second embodiment of the present invention. In the fifth position, 21 is a microphone, a log processor, 22 is a memory space, and 23 is an IO
space, 24#"t display device, 25 keyboard, 26 interface area, 27 display control program, 28 keyboard control program, 29 each ellipse program, 30 display control register, 3
1-line keyboard control register group, 32 flip-flops, 33 is OR circuit s Tm and Trdd interrupt 7: required i
r7. No. 3 and 34 respectively indicate the DSP-KB i:y Tough Ace area. Note that 1) SP is Displa.
y is an abbreviation, and KB is an abbreviation for Keyboard.

As in the first embodiment, the microprocessor 21 has multiple interrupt levels, and the memory space 22 has an interface area 26 . Display control program 27.
Keyboard control program 28 and various programm 2
In the IO space 23, a display control register group 3], a keyboard control register group, etc. are arranged. Display control register group 3
0 is for controlling the display device 24, and the keyboard control register 31 is for controlling the keyboard 25. An interrupt request signal 'caused by the display device is sent out on the signal line TnJ:K. O
An interrupt factor inherent to the keyboard (for example, an interrupt request signal manually generated by a key) is input to the upper input terminal of the R circuit 33, and the contents of the KFi flip flop 32 are input to the lower input terminal of the OR circuit 32. The output of the OR (b) path 33 is sent onto the interrupt line 16. The relationship between the display device [24] and the keyboard 25 is very complicated. For example, when a kana field is set on the display screen using a gramogram and the cursor is positioned in the kana field, it is necessary to set the keyboard 25 to the kana mode. When the operator enters Kana mode and presses the alphabet/kana key, kana characters are automatically input. That is, the operation of the shift key can be omitted.

FIG. 6/fi shows the configuration of the second embodiment of the second embodiment.

When the display control program is executed.

The following processing is performed.

■ Display the data on the display screen.

■ Is it necessary to set the keyboard mode?

Find out whether or not. If Yes, process ■.

If it's no, it's over. Note that end has the same meaning as return.

■ Specify the mode setting in the DSP-KB interface area.

■ Turn on the flip-prop 32, which causes a keyboard interrupt, and then set the fK end.

When the 7th rip-flop 32 is turned on, the interrupt request signal on the 1st interrupt request signal line becomes logic "1". This interrupt request signal has an interrupt level m8. Interrupt level m has a higher priority than interrupt level n.

The microprocessor 1 has an interrupt request signal Tm of logic "1".
'', the interrupt handling routine in the keyboard control program is executed on the condition that there is no higher interrupt request. This interrupt processing routine performs the following processing.

■ Check whether the key was manually interrupted or not. If Yes, the process of @ is performed, and if the result is No, the process of ■ is performed.

■ Turn off the flip-flop 32 that causes the interrupt.

■ IJ-view the DSP-KB interface area. ■ Check whether there is a mode setting specification in the DSP-KB interface area. If Yes, perform the @ process, and if No, perform the ■ process.

■ Perform processing other than key mode mode settings.

@ DSP-KB Inter → Clear the ace area.

End.

■ Set the key mode and perform the primary 0 processing.

■ Perform key manual processing and then end.

According to the second embodiment, IJ is limited to interrupts caused by the interrupt request signal Tm, and complicated control between interrupt levels is eliminated, which simplifies the program. ′ is there.

(6) Effects of the Invention As is clear from the above explanation, according to the present invention, complicated control between one interrupt level is eliminated, and the control effort and input are limited, so program control is possible. Effects such as simplification and commonization can be obtained. Furthermore, processes that were previously executed with a high priority can now be processed with a low priority.
It is also possible to prevent overruns.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a hardware configuration of a first embodiment of the present invention, FIGS. 2(A) and (B) are diagrams showing an example of a software configuration of a first embodiment of the present invention, and FIG. 4 is a time chart showing conventional input/output processing, FIG. 4 is a time chart showing input/output processing according to the present invention, FIG. 5 is a diagram showing the hardware configuration of the second embodiment of the present invention, and FIG. FIG. 3 is a diagram showing a software configuration of a second embodiment of the invention. 1...Microprocessor, 2...Memory space. 3... ■0 space, 4... Floppy disk device. 5... Display device, 6... Printer device, 7
. . . Interface area, 8 . . FPD (70-tube disk) control program, 9 . DESCRIPTION OF SYMBOLS 11... Final processing program, 12... Various programs, 13... FPD III control register group, 1
4...Display control register, 15...Printer control register% 16...Flip flow'tub,
17...FPDi connection flutter flag area...Display termination flag area, 19...P2 nonta termination flag area, T or Ti...Interrupt request signal line %21-
...Microprocessor, 22...Memory space, 2
3... IO space, 24... Display device, 25
...Keyboard, 26...Interface area, 2
7... Display control program, 28... Keyboard control program, 29... Rights program, 3
0...Display control register, 31...Keyboard control register group, 32...Slip contest flop,
33...OR circuit, Tm and Tn...interrupt request signal line, 34...DSP-KB interface area. Patent applicant: Uzutsuk Electronics Industry Co., Ltd. Kuto, patent attorney
Kyotani 4 parts 1 person and 1 figure

Claims (1)

[Claims] In a data processing system having a microprocessor with multiple interrupt levels, a flip-flop is provided to generate an interrupt request signal for a particular interrupt level, and the seven flip-flops are controlled by the other interrupt level. This is an input/output control method that is characterized by being able to perform the following functions.