JPS5882336A - Information array device - Google Patents

Abstract

PURPOSE:To store an array of numbers of digital information signals in increasing or decreasing order with regard to components of a specific item by rearranging components belonging to a specific item in increasing or decreasing order through signal processing. CONSTITUTION:Output time series signals and input time series information signals of sequence shift registers SR1-SRn are compared mutually by comparators CM1-CMn. According to comparison results, large and small relations and coincidences between digital information signals in outut time series signals and input time series information signals of said sequence shift registers are stored in large and small relation storage devices CF1-CFn and coincidence storage devices FEQ1-FEQn respectively. According to their storage contents, addresses of the storage devices are set by address setters AD1-ADn. On the other hand, the output time series signal of a total shift register SR0 for storing the input time series information signal consisting of sequences is converted into a simultaneous signal of every prescribed unit, which is inputted to a series converter SIPO for supply to the storage devices.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an information sorting device that focuses on parts and rearranges them in ascending or descending order, and is particularly aimed at shortening the time required for the arrangement.

First, we will define some terms used below.

Here, we will deal with a set of data like the one shown in Figure 1. here,
a, , a2, b, , b2, --, etc. are a set of bits, which are significantly the smallest units of information, and are called components. A collection of components (al, bl.

..., zl) will be called a set. In addition, a collection of members of the same species (for example, (, b, , b2..., bn
) are called items (a, , b, ,
...zl) to (an, bn, ...zn) are called files.

Generally, in order to focus on a specific item of information in a file and arrange the sets in order of size according to the size of the components, it is necessary to compare the mutual ratio of a large number of information signals! Since it is necessary to perform the bite repeatedly, there is a problem in that it takes time to repeatedly execute the bite using a microprogram or the like.

An object of the present invention is to solve the above-mentioned conventional problems, and to arrange a large number of digital information signals contained in an input information signal in order of magnitude with respect to the components of a specific item by signal processing using a simple procedure. An object of the present invention is to provide an information alignment device that can be stored.

The present invention pays attention to the magnitude of the values of components belonging to specific items in a set, and applies silk (a-work, b□, ・
..., Z□) through a simple signal processing process to obtain a predetermined result.

That is, the information aligning device according to the present invention only reads the entire information area of the input (3) information signal twice.
It is possible to arrange the human information signals in a desired order of size, that is, in order of increasing size or in order of decreasing size.

The present invention will be described in detail below with reference to the drawings.

First, an example of the configuration of the information sorting device of the present invention is shown in Fig. 92.

An example of the configuration of input information signals to be aligned by the apparatus of the present invention is shown in FIG.

Illustrated human power digital information I β 1jWN, magnetic deso.

R4 on a recording medium that records bits in series, such as a magnetic disk.
, I'l4. "'+ Zll R2+ b2. "'+
Z2. """"""'"n'bn,...,zn
Assume that [lXMa is in the order of . Therefore, when reading data from such a recording medium and supplying it as an input information signal to the present apparatus, the weights expressed in the order of Ul and the subscript number are removed first.

Now, set spout 17 to m LJ (b,, b2.--tbn) (a□.

item (b,, b,
,, -...,bn), the human nature of B engineering, < is the silk that takes a lot of steps (ai, bi+...
, zi) shall be rearranged.

(g) When such input information signal groups are sequentially supplied as input signals IN to the apparatus of the present invention starting from a in the order of weight as described above, the arrangement of the information signals by the apparatus of the present invention is as described above. This is done by repeatedly inputting the entire range of the input information signal group twice, and the first time is
,... 9bn value of humanity - or procedure, , b2.
..., bn are stored in shift registers SR1-5RnO. Each series shift register SRi accommodates them in order of weight, and the final series shift register SRn accommodates the one with the maximum weight or the minimum weight. Then,
In the second time, the sets (a, bi, . . . , 2□) are stored in the external random access memory RAM for each series by using the results of the /th division into each series shift register SRn. The data is rearranged in the order of the weight represented by the subscript i and written sequentially.

To explain each component in the illustrated circuit configuration for arranging such information signals, the general shift register S
'E3o has a capacity sufficient to accommodate bits in the entire area of the set (ai, bi, .

This is for converting serial digital data into parallel digital data for each byte or word of a group of digital information signals temporarily stored in the memory, and simultaneously writing each unit to the random access memory RAM. , is for sequentially outputting the lower addresses when each unit of parallel digital data from the serial/parallel converter 5IPO is sequentially applied to the random access memory IJ RAM, and the upper address is set for the lower address. In each system of multiple systems of address setting circuits provided as many as the number of subscripts i representing weights, each system shift register SR4 (i = /~n) receives input information signal groups (ai, bi, . . . , 2ρ, a specific item b
In order to accommodate only part i in order of weight, each has a capacity of m bits or more.
- The bit portion of SRj is shifted periodically for a specified period of time. Each changeover switch SW□- connects the input to each series shift register SRi to the human input signal group IN, the output signal 0UT (i-/) of the previous series shift register 5R (i-/), and the output signal 0UT (i-/) of the corresponding stage. This is for switching to and selecting one of the output signals 0UTi of the series shift register SR4, and the logic for this selection is based on the magnitude memory OF (i-/) of the previous stage and the magnitude memory 'aOF of the relevant stage. □, and the logic is shown in Figure 3 in the case of a great wish, and in Figure 9 in the case of a katoshi or an irregularity, respectively.

Next, each comparator G compares the input information signal 1IN and the output signal OU'I'□- of each series shift register SRi bit by bit, and stores the comparison result in each size. Each of the large and small memory devices GFi is outputted to the memory device GFi, and each of the large and small memory devices GFi is
Each series shift register SRi operates only when each digital information signal b□ of a particular series of interest arrives.
The result of the comparison between the output signal 0UTi of the output signal 0UTi and its digital information signal
This is for storing information according to the previous state of F1 itself, and IN>5R4(OUTi), IN2SR(O
This is to store data separately in two types of magnitude relationship states: UT (UT) and IN < SR (OUTi), and each address setter AI]i randomly selects a This is for setting the upper address of the access memory RAM, and each address setting device AD
1 to ADn have fixed values of (n-/) to 0.

Next, the operation of the information sorting device of the present invention including the above-mentioned components will be explained step by step.

Step 1: The stored contents of each series shift register SR4 are all set to "/" when performing a grand arrangement, and are all set to 0" when an irregular arrangement is to be performed.

Step 2: IN = 5Rj-
(0UTi).

Step 3: Start inputting a bit string to IN, operate the SR1 system at the determination time before the start of the item of interest, and shift the information until just before the item of interest bi starts.

Step 'l': Bit information of the item of interest bi from IN and output signal 0U of series shift register SRi
T4 is compared, and the state of the size memory OFi is changed according to the result of the comparison. The logic of the state transition is as shown in FIG. No yo? , in the figure, X is IN > 0UTi, IN = O
UTi, IN < 0UTi. When arranging the grand wishes, the selector switch 5Wj- of the relevant stage is switched according to the state of the size memory CFi and (3F(i-/)) of the relevant stage and the preceding stage according to the logic shown in the third diagram. When performing out-of-order sorting, switching is performed according to the logic shown in FIG.

Step j: Increment only the memory booter/hit of the series shift register SR.

Step B: Repeat step (9) until the digital information of interest has been received.

Step 7 Shifting is continued until the bit length of the shift register SRi is filled while holding the two large and small memory (3Fi) without transitioning.

Step g: From now on, 2 of group (ai, b, ..., zi)
Nothing works when reading 0 ends.

Step q: Repeat steps 3 to g at the trench where the final digital information signal zn enters.

Through the process up to step q, each series shift register SR4 accommodates the aligned attention information signal bz and the one with meaningless data attached before and after it, and the series shift register 5RnO at the final stage stores the following: Attention information signal b
Of z, the largest one is stored when arranging the big wishes, and the smallest one is stored when the arranging is done out of order. When sorting, the smallest one is accommodated, and when doing an unordered sorting, the largest one is accommodated.
7). In this state, the input of the /th all-area input information signal is completed, and the process moves to the λth time.

Step IO=changeover switch SWi, from now on, li side,
That is, it is fixed to the side to which the output signal 0UTi- of the series shift register SR of the relevant stage is input.

Step ll: Large/small memory (all states of EFi are stored in
-3R (OUTi).

Step/2: Start inputting input information to IN and store it in shift register SRo.

Step/3: Start operating each series shift register SR, to SRn at the same timing as step 3 above.

data is itself Shift register SRi where the body is stored Loop inside. shift register Continue to input data to SRo.

Step/Ri: Only while the bit string to be passed to the item S is flowing, the comparator CMi and the magnitude memory QF are operated to compare the data in each series shift register SRj with the IN data, The result is left in the size memory OFi. During this time, the changeover switch SWi is not changed, and the data in the series shift register SRi loops by itself. Continue inputting INN data to SRO.

Step /S: Stops the operation of the comparator GMi and the magnitude storage CFi, and continues shifting only the remaining bit portion of the shift register SRi.

Step B: Soft register SRj, comparator CM'
j.

The operation of the large/small memory device OFj is determined, and the shift register SRo continues to be manually inputted until the last 2nd shift of one set is completed.

Step/7: I N = S in the size memory CFi-
The coincidence memory FEQ,i is set to "/" corresponding to the state of Ri, (OU'I'i), and the coincidence memory FEQ,i is set to "O" for the other states.

Step /g = While executing the above-described sequential steps l/ to /7, the output of the address setter ADi corresponding to "l" of the coincidence memory FEQi is set as the upper address, and the output of the counter OF The stored data in the general shift register SRo is stored in the external random access memory RAM K 9 through the serial/parallel converter 5IPO with .

Step/q F final input information signal (an, bn, ・
. . . The process of steps /l to Ig is repeated until the process of 2n) is completed.

By the above operation, the external random access memory RA
Input information signals (al, bi, etc.) of all regions are included in M.

zl) arranged in the ascending or descending order of the items bi of the particular series of interest can be stored.

As is clear from the above description, according to the present invention, it is possible to obtain information about a desired series by a simple operation (13) of repeating twice the entire range of a group of human-powered digital information signals of multiple series. Humans can also generate a group of information signals arranged in the smallest order.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the structure of the input information signal group of the information sorting device of the present invention, Fig. 2 is a block diagram showing the same circuit structure, and Fig. 3 is a block diagram showing the same circuit structure. A diagram showing the operating logic of the switches when they are arranged in order, Fig. 2 is a diagram showing the operating logic of the changeover switches when they are arranged out of order, and Fig. S is the logic of the state transition of the large and small memory devices in the same circuit configuration. FIG. SRa...General shift register, 5IPO...Serial to parallel converter, QF...Counter, 5
Ri-(SR1 to 5Rn)... Series shift register,
5Wi (SW1-5Wn)...Selector switch, CJ
(OM+ ~GMn) - Comparator, 0Fi (OFl ~
0Fn) -... Size memory, FEQ: 1 (FEQ+
~FEQn) - coincidence store, ADi (AD1~ADn
) - address setter, BUFF...buffer. (/the law of nature)

Claims (1)

[Claims] A general shift register capable of storing input time-series information signals consisting of a plurality of series having the same number of digital information signals for each series, and an output time-series signal of the general shift register for each predetermined unit. a serial-to-parallel converter that converts the signal into a simultaneous signal and supplies it to a storage device; and the storage device that determines the order of magnitude of the digital information signal for a predetermined series and stores the simultaneous signal from the serial-to-parallel converter. the number of address setting circuits for setting the addresses of the addresses, and a counter for sequentially setting the lower addresses for the addresses; a changeover switch that switches between the output time series signal of the series shift register of the previous stage, the output time series signal of the series shift register of the previous stage, and the input time series information signal and supplies it to the series shift register of the stage, and the output time of the series shift register of the stage of the stage; a comparator that compares a sequence signal signal with the input time-series information signal; and a comparator that compares a sequence signal signal with the input time-series information signal, and a digital information in the output time-series signal of the sequence shift register of the relevant stage and the input time-series information signal according to the comparison result of the comparator. The device is constructed of a size storage device that stores mutual magnitude relationships with respect to signals, a coincidence storage device that stores mutual coincidence, and an address setter that sets the address of the storage device according to the stored contents of these storage devices. An information sorting device characterized by: